STM32WL55CCU6 STM32 32-bit Arm Cortex MCUs by STMicroelectronics
Sub-GHz Wireless Microcontrollers. Dual-core Arm Cortex-M4/M0+ @48 MHz with 256 Kbytes of Flash memory, 64 Kbytes of SRAM. LoRa, (G)FSK, (G)MSK, BPSK modulations. AES 256-bit. Multiprotocol System-on-Chip.
| Status: | Active |
|---|---|
| Series: | STM32WL55CC |
| RoHS: | Compliant |
Where to Buy
Prices starting from US$4.09
| Distributor | Stock | ||
|---|---|---|---|
|
RS
from US$7.14
|
10
in stock
|
Buy Now |
|
Future Electronics
from US$4.09
|
17,940
in stock
|
Buy Now |
|
element14
from US$5.31
|
6,330
in stock
|
Buy Now |
|
Farnell
from US$5.33
|
5,977
in stock
|
Buy Now |
|
Newark Electronics
from US$7.75
|
115
in stock
|
Buy Now |
|
EBV Elektronik
-
|
2,340
in stock
|
Buy Now |
|
Avnet Silica
-
|
-
|
Buy Now |
Features
| Includes ST state-of-the-art patented technology |
| Radio Frequency range: 150 MHz to 960 MHz Modulation: LoRa®, (G)FSK, (G)MSK and BPSK RX sensitivity: –123 dBm for 2-FSK(at 1.2 Kbit/s), –148 dBm for LoRa® (at 10.4 kHz, spreading factor 12) Transmitter high output power, programmable up to +22 dBm Transmitter low output power, programmable up to +15 dBm Compliant with the following radio frequency regulations such as ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101 and the Japanese ARIB STD-T30, T-67, T-108 Compatible with standardized or proprietary protocols such as LoRaWAN®, Sigfox™, W-MBus and more (fully open wireless system-on-chip) |
| Frequency range: 150 MHz to 960 MHz |
| Modulation: LoRa®, (G)FSK, (G)MSK and BPSK |
| RX sensitivity: –123 dBm for 2-FSK(at 1.2 Kbit/s), –148 dBm for LoRa® (at 10.4 kHz, spreading factor 12) |
| Transmitter high output power, programmable up to +22 dBm |
| Transmitter low output power, programmable up to +15 dBm |
| Compliant with the following radio frequency regulations such as ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101 and the Japanese ARIB STD-T30, T-67, T-108 |
| Compatible with standardized or proprietary protocols such as LoRaWAN®, Sigfox™, W-MBus and more (fully open wireless system-on-chip) |
| Ultra-low-power platform 1.8 V to 3.6 V power supply –40 °C to +105 °C temperature range Shutdown mode: 31 nA (VDD = 3 V) Standby (+ RTC) mode:360 nA (VDD = 3 V) Stop2 (+ RTC) mode: 1.07 µA (VDD = 3 V) Active-mode MCU: < 72 µA/MHz (CoreMark®) Active-mode RX: 4.82 mA Active-mode TX: 15 mA at 10 dBm and 87 mA at 20 dBm (LoRa® 125 kHz) |
| 1.8 V to 3.6 V power supply |
| –40 °C to +105 °C temperature range |
| Shutdown mode: 31 nA (VDD = 3 V) |
| Standby (+ RTC) mode:360 nA (VDD = 3 V) |
| Stop2 (+ RTC) mode: 1.07 µA (VDD = 3 V) |
| Active-mode MCU: < 72 µA/MHz (CoreMark®) |
| Active-mode RX: 4.82 mA |
| Active-mode TX: 15 mA at 10 dBm and 87 mA at 20 dBm (LoRa® 125 kHz) |
| Core 32-bit Arm® Cortex®-M4 CPU Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 48 MHz, MPU and DSP instructions 1.25 DMIPS/MHz (Dhrystone 2.1) 32-bit Arm®Cortex®-M0+ CPU Frequency up to 48 MHz, MPU 0.95 DMIPS/MHz (Dhrystone 2.1) |
| 32-bit Arm® Cortex®-M4 CPU Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 48 MHz, MPU and DSP instructions 1.25 DMIPS/MHz (Dhrystone 2.1) |
| Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 48 MHz, MPU and DSP instructions |
| 1.25 DMIPS/MHz (Dhrystone 2.1) |
| 32-bit Arm®Cortex®-M0+ CPU Frequency up to 48 MHz, MPU 0.95 DMIPS/MHz (Dhrystone 2.1) |
| Frequency up to 48 MHz, MPU |
| 0.95 DMIPS/MHz (Dhrystone 2.1) |
| Security and identification Hardware encryption AES 256-bit True random number generator (RNG) Sector protection against read/write operations (PCROP, RDP, WRP) CRC calculation unit Unique device identifier (64-bit UID compliant with IEEE 802-2001 standard) 96-bit unique die identifier Hardware public key accelerator (PKA) Key management services Secure sub-GHz MAC layer Secure firmware update (SFU) Secure firmware install (SFI) |
| Hardware encryption AES 256-bit |
| True random number generator (RNG) |
| Sector protection against read/write operations (PCROP, RDP, WRP) |
| CRC calculation unit |
| Unique device identifier (64-bit UID compliant with IEEE 802-2001 standard) |
| 96-bit unique die identifier |
| Hardware public key accelerator (PKA) |
| Key management services |
| Secure sub-GHz MAC layer |
| Secure firmware update (SFU) |
| Secure firmware install (SFI) |
| Supply and reset management High-efficiency embedded SMPS step-down converter SMPS to LDO smart switch Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds Ultra-low-power POR/PDR Programmable voltage detector (PVD) VBAT mode with RTC and 20x32-bit backup registers |
| High-efficiency embedded SMPS step-down converter |
| SMPS to LDO smart switch |
| Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds |
| Ultra-low-power POR/PDR |
| Programmable voltage detector (PVD) |
| VBAT mode with RTC and 20x32-bit backup registers |
| Clock sources 32 MHz crystal oscillator TCXO support: programmable supply voltage 32 kHz oscillator for RTC with calibration High-speed internal 16 MHz factory trimmed RC (± 1 %) Internal low-power 32 kHz RC Internal multi-speed low-power 100 kHz to 48 MHz RC PLL for CPU, ADC and audio clocks |
| 32 MHz crystal oscillator |
| TCXO support: programmable supply voltage |
| 32 kHz oscillator for RTC with calibration |
| High-speed internal 16 MHz factory trimmed RC (± 1 %) |
| Internal low-power 32 kHz RC |
| Internal multi-speed low-power 100 kHz to 48 MHz RC |
| PLL for CPU, ADC and audio clocks |
| Memories 256-Kbyte Flash memory 64-Kbyte RAM 20x32-bit backup register Bootloader supporting USART and SPI interfaces OTA (over-the-air) firmware update capable Sector protection against read/write operations |
| 256-Kbyte Flash memory |
| 64-Kbyte RAM |
| 20x32-bit backup register |
| Bootloader supporting USART and SPI interfaces |
| OTA (over-the-air) firmware update capable |
| Sector protection against read/write operations |
| Rich analog peripherals (down to 1.62 V) 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling, conversion range up to 3.6 V 12-bit DAC, low-power sample-and-hold 2x ultra-low-power comparators |
| 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling, conversion range up to 3.6 V |
| 12-bit DAC, low-power sample-and-hold |
| 2x ultra-low-power comparators |
| System peripherals Mailbox and semaphores for communication between Cortex®-M4 and Cortex®-M0+ firmware |
| Mailbox and semaphores for communication between Cortex®-M4 and Cortex®-M0+ firmware |
| Controllers 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART, USART, AES and timers 2x USART (ISO 7816, IrDA, SPI) 1x LPUART (low-power) 2x SPI 16 Mbit/s (1 over 2 supporting I2S) 3x I2C (SMBus/PMBus®) 2x 16-bit 1-channel timer 1x 16-bit 4-channel timer (supporting motor control) 1x 32-bit 4-channel timer 3x 16-bit ultra-low-power timer 1x RTC with 32-bit sub-second wakeup counter 1x independent SysTick 1x independent watchdog 1x window watchdog |
| 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART, USART, AES and timers |
| 2x USART (ISO 7816, IrDA, SPI) |
| 1x LPUART (low-power) |
| 2x SPI 16 Mbit/s (1 over 2 supporting I2S) |
| 3x I2C (SMBus/PMBus®) |
| 2x 16-bit 1-channel timer |
| 1x 16-bit 4-channel timer (supporting motor control) |
| 1x 32-bit 4-channel timer |
| 3x 16-bit ultra-low-power timer |
| 1x RTC with 32-bit sub-second wakeup counter |
| 1x independent SysTick |
| 1x independent watchdog |
| 1x window watchdog |
| Up to 43 I/Os, most 5 V-tolerant |
| Development support Serial-wire debug (SWD), JTAG Dual CPU cross trigger capabilities |
| Serial-wire debug (SWD), JTAG |
| Dual CPU cross trigger capabilities |
| All packages ECOPACK2 compliant |
Resources
Product Specifications |
|---|
| DS13293 Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0+ LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM |
Programming Manuals |
|---|
| PM0223 Cortex®-M0+ programming manual for STM32L0, STM32G0, STM32WL and STM32WB Series |
| PM0214 STM32 Cortex®-M4 MCUs and MPUs programming manual |
Errata Sheets |
|---|
| ES0500 STM32WL55xx, STM32WL54xx device errata |
Alternative Descriptions
| STM32WL Series LPWAN Dual Core ARM Cortex-M4/M0 + Full Set of Modulation + LoRa | Future Electronics |
| MCU, 32BIT, 256KB, UFQFPN-48 | element14 |
| Mcu, 32Bit, 256Kb, Ufqfpn-48 Rohs Compliant: Yes |Stmicroelectronics STM32WL55CCU6 | Newark Electronics |
| STM32WL55CCU6, 32-Bit LPWAN Lora MCU | RS |
| MCU-Application Specific 32 bit, 48 MHz, 1.8 V to 3.6 V in, 256KB, UFQFPN-48 | EBV Elektronik |
Frequently Asked Questions
Where can I find additional details, specifications and documents for a STM32WL55CCU6?
Additional datasheets, footprints and schematics for STM32WL55CCU6 are listed on our Part Details page. You can also find images and similar parts to STM32WL55CCU6 on this page.
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What category does STM32WL55CCU6 fall under?
The STM32WL55CCU6 is listed under Microcontrollers & Microprocessors > STM32 32-bit Arm Cortex MCUs > STM32 Wireless MCUs > STM32WL Series > STM32WL5x.
Can I view similar or alternative parts?
You can view similar parts to STM32WL55CCU6 when available in the STM32WL5x range under the specifications section at the bottom of the details page.
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Is the STM32WL55CCU6 RoHS compliant?
Yes. This part has been flagged as RoHS Compliant by STMicroelectronics.
Which authorised distributors for STM32WL55CCU6 have stock available?
Authorised distributors including Future Electronics, element14, Farnell, Newark Electronics and RS have stock available or on a lead time for STM32WL55CCU6.
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