MC100EP195FAG Clock & Data Distribution by ON Semiconductor

3.3 V ECL Programmable Delay Chip

Semiconductors - ICs
> Clock,Timing & Frequency Management
> Delay Lines
Status: Active
Series: MC100EP195
RoHS: Compliant
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NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the data sheet logic diagram. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(0:9) which are latched on chip by a high signal on the latch enable (LEN) control. The MC10/100EP195 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in the data sheet. Because the EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Select input pins D0-D10 may be threshold controlled by combinations of interconnects between VEF (pin 7) and VCF (pin 8) for CMOS, ECL, or TTL level signals. For CMOS input levels, leave VCF and VEF open. For ECL operation, short VCF and VEF (pins 7 and 8). For TTL level operation, connect a 1.5 V supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 1.5k Ohm or 500 Ohm resistor between VCF and VEE for 3.3 V or 5.0 V power supplies, respectively. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or

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Features

Maximum Frequency > 1.2 Ghz Typical
Programmable Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range: VCC = 3.0 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the ENbar Pin Will Force Q to Logic Low
D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs.
VBB Output Reference Voltage
Pb-Free Packages are Available
Applications
Automated Test Equipement (ATE)
End Products
General Purpose Data and Clock Interface

Specifications

Description MC100EP195
Compliance Pb-free Halide free
Input Level CML ECL
Output Level ECL
VCC Typ (V) 3.3
fMax Typ (MHz) 1200
td(prog) Min (ns) 7.85
td(prog) Max (ns) 10.95
td(step) Typ (ps) 14
tJitter Typ (ps) 1.16
tR & tF Max (ps) 135 200
Package Type LQFP-32

Alternative Descriptions

Ic, Sm, Logic, Ecl, Clock Dist | Newark Electronics
IC, SM, LOGIC, ECL, CLOCK DIST | element14
ON Semiconductor, MC100EP195FAG | RS
Active Programmable Delay Line 1-IN 0.01ns ABS 12.2ns MAX 32-Pin LQFP Tray | Avnet America
MC100EP195 Series 1.2 GHz 3.6 V SMT ECL Programmable Delay Chip - LQFP-32 | Future Electronics

Frequently Asked Questions

Where can I find additional details, specifications and documents for a MC100EP195FAG?

Additional datasheets, footprints and schematics for MC100EP195FAG are listed on our Part Details page. You can also find images and similar parts to MC100EP195FAG on this page.

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What category does MC100EP195FAG fall under?

The MC100EP195FAG is listed under Timing, Logic & Memory > Clock & Data Distribution > Skew Management.

Can I view similar or alternative parts?

You can view similar parts to MC100EP195FAG when available in the Skew Management range under the specifications section at the bottom of the details page.

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Is the MC100EP195FAG RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by ON Semiconductor.

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