AD9557BCPZ Clock Synchronization by Analog Devices

Status: Production
Series: AD9557
RoHS: Compliant
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The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9557 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9557 operates over an industrial temperature range of −40°C to +85°C. If more inputs/outputs are needed, refer to the AD9558 for the four-input/six-output version of the samedevice.

Where to Buy

Prices starting from US$13.90

Distributor Stock
Logo for Analog Devices
Analog Devices
from US$19.26
4,065
in stock
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Logo for Chip One Stop
Chip One Stop
from US$13.90
16
in stock
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Logo for Richardson RFPD
Richardson RFPD
from US$27.15
-
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Features

Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually no disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, G.824, G.825, and G.8261
Auto/manual holdover and reference switchover
2 reference inputs (single-ended or differential)
Input reference frequencies: 2 kHz to 1250 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
20-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs
Output frequencies: 360 kHz to 1250 MHz
Programmable 17-bit integer and 23-bit fractional feedback divider in digital PLL
Programmable digital loop filter covering loop bandwidths from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking)
Low noise system clock multiplier
Frame sync support
Adaptive clocking
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Pin program function for easy frequency translation configuration
Software controlled power-down
40-lead, 6 mm × 6 mm, LFCSP package

Alternative Descriptions

Multi-protocol line card clock | Analog Devices
LOGIC AND TIMING | Richardson RFPD


Frequently Asked Questions

Where can I find additional details, specifications and documents for a AD9557BCPZ?

Additional datasheets, footprints and schematics for AD9557BCPZ are listed on our Part Details page. You can also find images and similar parts to AD9557BCPZ on this page.

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What category does AD9557BCPZ fall under?

The AD9557BCPZ is listed under Clock Synchronization.

Can I view similar or alternative parts?

You can view similar parts to AD9557BCPZ when available in the Clock Synchronization range under the specifications section at the bottom of the details page.

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Is the AD9557BCPZ RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by Analog Devices.

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Authorised distributors including Analog Devices, Chip One Stop and Richardson RFPD have stock available or on a lead time for AD9557BCPZ.

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