Status: | Active |
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Series: | STM32MP151A |
RoHS: | Compliant |
Includes ST state-of-the-art patented technology |
Core 32-bit Arm® Cortex®-A7 L1 32-Kbyte I / 32-Kbyte D 256-Kbyte unified level 2 cache Arm® NEON™ and Arm® TrustZone® 32-bit Arm® Cortex®-M4 with FPU/MPU Up to 209 MHz (Up to 703 CoreMark®) |
32-bit Arm® Cortex®-A7 L1 32-Kbyte I / 32-Kbyte D 256-Kbyte unified level 2 cache Arm® NEON™ and Arm® TrustZone® |
L1 32-Kbyte I / 32-Kbyte D |
256-Kbyte unified level 2 cache |
Arm® NEON™ and Arm® TrustZone® |
32-bit Arm® Cortex®-M4 with FPU/MPU Up to 209 MHz (Up to 703 CoreMark®) |
Up to 209 MHz (Up to 703 CoreMark®) |
Memories External DDR memory up to 1 Gbyte up to LPDDR2/LPDDR3-1066 16/32-bit up to DDR3/DDR3L-1066 16/32-bit 708 Kbytes of internal SRAM: 256 Kbytes of AXI SYSRAM + 384 Kbytes of AHB SRAM + 64 Kbytes of AHB SRAM in Backup domain and 4 Kbytes of SRAM in Backup domain Dual mode Quad-SPI memory interface Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC |
External DDR memory up to 1 Gbyte up to LPDDR2/LPDDR3-1066 16/32-bit up to DDR3/DDR3L-1066 16/32-bit |
up to LPDDR2/LPDDR3-1066 16/32-bit |
up to DDR3/DDR3L-1066 16/32-bit |
708 Kbytes of internal SRAM: 256 Kbytes of AXI SYSRAM + 384 Kbytes of AHB SRAM + 64 Kbytes of AHB SRAM in Backup domain and 4 Kbytes of SRAM in Backup domain |
Dual mode Quad-SPI memory interface |
Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC |
Security/safety TrustZone® peripherals, active tamper Cortex®-M4 resources isolation |
TrustZone® peripherals, active tamper |
Cortex®-M4 resources isolation |
Reset and power management 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) POR, PDR, PVD and BOR On-chip LDOs (RETRAM, BKPSRAM, USB 1.8 V, 1.1 V) Backup regulator (~0.9 V) Internal temperature sensors Low-power modes: Sleep, Stop and Standby DDR memory retention in Standby mode Controls for PMIC companion chip |
1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) |
POR, PDR, PVD and BOR |
On-chip LDOs (RETRAM, BKPSRAM, USB 1.8 V, 1.1 V) |
Backup regulator (~0.9 V) |
Internal temperature sensors |
Low-power modes: Sleep, Stop and Standby |
DDR memory retention in Standby mode |
Controls for PMIC companion chip |
Low-power consumption Total current consumption down to 2 µA (Standby mode, no RTC, no LSE, no BKPSRAM, no RETRAM) |
Total current consumption down to 2 µA (Standby mode, no RTC, no LSE, no BKPSRAM, no RETRAM) |
Clock management Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator 5 × PLLs with fractional mode |
Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator |
External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator |
5 × PLLs with fractional mode |
General-purpose input/outputs Up to 176 I/O ports with interrupt capability Up to 8 secure I/Os Up to 6 Wakeup, 3 tampers, 1 active tamper |
Up to 176 I/O ports with interrupt capability Up to 8 secure I/Os Up to 6 Wakeup, 3 tampers, 1 active tamper |
Up to 8 secure I/Os |
Up to 6 Wakeup, 3 tampers, 1 active tamper |
Interconnect matrix 2 bus matrices 64-bit Arm® AMBA® AXI interconnect, up to 266 MHz 32-bit Arm® AMBA® AHB interconnect, up to 209 MHz |
2 bus matrices 64-bit Arm® AMBA® AXI interconnect, up to 266 MHz 32-bit Arm® AMBA® AHB interconnect, up to 209 MHz |
64-bit Arm® AMBA® AXI interconnect, up to 266 MHz |
32-bit Arm® AMBA® AHB interconnect, up to 209 MHz |
3 DMA controllers to unload the CPU 48 physical channels in total 1 × high-speed general-purpose master direct memory access controller (MDMA) 2 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management |
48 physical channels in total |
1 × high-speed general-purpose master direct memory access controller (MDMA) |
2 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management |
Up to 35 communication peripherals 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external clock) 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) SPDIF Rx with 4 inputs HDMI-CEC interface MDIO Slave interface 3 × SDMMC up to 8-bit (SD / e•MMC™/ SDIO) 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously or 1 × USB 2.0 high-speed Host+ 1 × USB 2.0 high-speed OTG simultaneously 10/100M or Gigabit Ethernet GMAC IEEE 1588v2 hardware, MII/RMII/GMII/RGMII 8- to 14-bit camera interface up to 140 Mbyte/s |
6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) |
4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) |
6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external clock) |
4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) |
SPDIF Rx with 4 inputs |
HDMI-CEC interface |
MDIO Slave interface |
3 × SDMMC up to 8-bit (SD / e•MMC™/ SDIO) |
2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously or 1 × USB 2.0 high-speed Host+ 1 × USB 2.0 high-speed OTG simultaneously |
or 1 × USB 2.0 high-speed Host+ 1 × USB 2.0 high-speed OTG simultaneously |
10/100M or Gigabit Ethernet GMAC IEEE 1588v2 hardware, MII/RMII/GMII/RGMII |
IEEE 1588v2 hardware, MII/RMII/GMII/RGMII |
8- to 14-bit camera interface up to 140 Mbyte/s |
6 analog peripherals 2 × ADCs with 16-bit max. resolution (12 bits up to 4.5 Msps, 14 bits up to 4 Msps, 16 bits up to 3.6 Msps) 1 × temperature sensor 2 × 12-bit D/A converters (1 MHz) 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 filters Internal or external ADC/DAC reference VREF+ |
2 × ADCs with 16-bit max. resolution (12 bits up to 4.5 Msps, 14 bits up to 4 Msps, 16 bits up to 3.6 Msps) |
1 × temperature sensor |
2 × 12-bit D/A converters (1 MHz) |
1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 filters |
Internal or external ADC/DAC reference VREF+ |
Graphics LCD-TFT controller, up to 24-bit // RGB888 up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @30 fps Pixel clock up to 90 MHz Two layers with programmable colour LUT |
LCD-TFT controller, up to 24-bit // RGB888 up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @30 fps Pixel clock up to 90 MHz Two layers with programmable colour LUT |
up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @30 fps |
Pixel clock up to 90 MHz |
Two layers with programmable colour LUT |
Up to 25 timers and 3 watchdogs 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input 2 × 16-bit advanced motor control timers 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) 5 × 16-bit low-power timers RTC with sub-second accuracy and hardware calendar 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor) 1 × SysTick M4 timer 3 × watchdogs (2 × independent and window) |
2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input |
2 × 16-bit advanced motor control timers |
10 × 16-bit general-purpose timers (including 2 basic timers without PWM) |
5 × 16-bit low-power timers |
RTC with sub-second accuracy and hardware calendar |
4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor) |
1 × SysTick M4 timer |
3 × watchdogs (2 × independent and window) |
Hardware acceleration HASH (MD5, SHA-1, SHA224, SHA256), HMAC 2 × true random number generator (3 oscillators each) 2 × CRC calculation unit |
HASH (MD5, SHA-1, SHA224, SHA256), HMAC |
2 × true random number generator (3 oscillators each) |
2 × CRC calculation unit |
Debug mode Arm® CoreSight™ trace and debug: SWD and JTAG interfaces 8-Kbyte embedded trace buffer |
Arm® CoreSight™ trace and debug: SWD and JTAG interfaces |
8-Kbyte embedded trace buffer |
3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user |
All packages are ECOPACK2 compliant |
Product Specifications |
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DS12500 Arm® Cortex®-A7 800 MHz + Cortex®-M4 MPU, TFT, 35 comm. interfaces, 25 timers, adv. analog |
Reference Manuals |
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RM0441 STM32MP151 advanced Arm®-based 32-bit MPUs |
Programming Manuals |
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PM0214 STM32 Cortex®-M4 MCUs and MPUs programming manual |
Errata Sheets |
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ES0438 STM32MP151x/3x/7x device errata |
MPU STM32MP151A RISC 32-Bit 650MHz 1.2V/1.35V/1.5V/1.8V/3.3V 361-Pin TFBGA Tray | EBV Elektronik |
STM32MP151AAC3, 32Bit Microcontrollers | RS |
Mpu, 32Bit, 650Mhz, -40 To 125Deg C | Newark Electronics |
MPU, 32BIT, 650MHZ, -40 TO 125DEG C | element14 |
Where can I find additional details, specifications and documents for a STM32MP151AAC3?
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Is the STM32MP151AAC3 RoHS compliant?
Yes. This part has been flagged as RoHS Compliant by STMicroelectronics.
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