SN65DSI84TPAPRQ1 Part Information
The SN65DSI84-Q1 DSI-to-LVDS bridge features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS or single-link LVDS with four data lanes per link. The SN65DSI84-Q1 device is well suited for WUXGA (1920 × 1080) at 60 frames per second (fps) with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces. The SN65DSI84-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a 0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
|Bridge Type||DSI to LVDS|
|Supply Voltage Min||1.65V|
|Supply Voltage Max||1.95V|
|Interface Case Style||HTQFP|
|No. of Pins||64Pins|
|Operating Temperature Min||-40°C|
|Operating Temperature Max||105°C|
|Automotive Qualification Standard||AEC-Q100|
|RoHS Phthalates Compliant||Yes|
|MSL||MSL 3 - 168 hours|
|SVHC||No SVHC (27-Jun-2018)|
Frequently Asked Questions
Where can I find additional details, specifications and documents for a SN65DSI84TPAPRQ1?
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What category does SN65DSI84TPAPRQ1 fall under?
The SN65DSI84TPAPRQ1 is listed under Electronic & Electrical Components > Semiconductors - ICs > Driver & Interface ICs.
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Is the SN65DSI84TPAPRQ1 RoHS compliant?
Yes. This part has been flagged as RoHS Compliant by Farnell.
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