PC16550DV/NOPB Part Information

Details for PC16550DV/NOPB by Texas Instruments

Electronic & Electrical Components > Semiconductors - ICs > Driver & Interface ICs

Part Description

The PC16550D device is an improved version of the original 16450 Universal Asynchronous Receiver/Transmitter (UART). Functionally identical to the 16450 on powerup (CHARACTER mode: can also be reset to 16450 Mode under software control) the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead. In this mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. All the logic is on chip to minimize system overhead and maximize system efficiency. Two pin functions have been changed to allow signalling of DMA transfers. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt).

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Part Features

  • Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data.
  • After Reset, All Registers Are Identical to the 16450 Register Set.
  • Capable of Running All Existing 16450 Software.
  • Complete Status Reporting Capabilities.
  • False Start Bit Detection.
  • Full Prioritized Interrupt System Controls.
  • Fully Programmable Serial-Interface Characteristics u2013 5-, 6-, 7-, or 8-Bit Characters u2013 Even, Odd, or No-Parity Bit Generation and Detection u2013 1-, 1 1/2-, or 2-Stop Bit Generation u2013 Baud Generation (DC to 1.5 M Baud).
  • Holding and Shift Registers in the 16450 Mode Eliminate the Need for Precise Synchronization Between the CPU and Serial Data.
  • In the FIFO(1) Mode Transmitter and Receiver Are Each Buffered With 16 Byte FIFOu2019s to Reduce the Number of Interrupts Presented to the CPU.
  • Independent Receiver Clock Input.
  • Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts.
  • Internal Diagnostic Capabilities u2013 Loopback Controls for Communications Link Fault Isolation u2013 Break, Parity, Overrun, Framing Error Simulation.
  • Line Break Generation and Detection.
  • MODEM Control Functions (CTS, RTS, DSR, DTR, RI, and DCD).
  • Pin for Pin Compatible With the Existing 16450 Except for CSOUT (24) and NC (29). The Former CSOUT and NC Pins Are TXRDY and RXRDY, Respectively.
  • Programmable Baud Generator Divides Any Input Clock by 1 to (216 u2013 1) and Generates the 16 u00d7 Clock.
  • TRI-STATE TTL Drive for the Data and Control Buses.

Part Specifications

No. of Channels 1 Channel, 1Channels
Data Rate 1.5Mbaud
Supply Voltage Min 4.5V
Supply Voltage Max 5.5V
Interface Case Style LCC
No. of Pins 44Pins
Operating Temperature Min 0°C
Operating Temperature Max 70°C
Product Range -
Automotive Qualification Standard -
RoHS Phthalates Compliant Yes
MSL MSL 1 - Unlimited
SVHC No SVHC (27-Jun-2018)
RoHS Compliant

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