Operating Range: |
Up to 40MIPS operation (at 3.0-3.6V) |
Industrial temperature range (-40u00b0C to +85u00b0C) |
Extended temperature range (-40u00b0C to +125u00b0C) |
High temperature range (-40u00b0C to +150u00b0C)High-Performance DSC CPU: |
Modified Harvard architecture |
C compiler optimized instruction set |
16-bit wide data path |
24-bit wide instructions |
Linear program memory addressing up to 4M instruction words |
Linear data memory addressing up to 64 Kbytes |
83 base instructions: mostly 1 word/1 cycle |
Sixteen 16-bit General Purpose Registers |
Two 40-bit accumulators: |
With rounding and saturation options |
Flexible and powerful addressing modes: |
Indirect, Modulo and Bit-Reversed |
Software stack |
16 x 16 fractional/integer multiply operations |
32/16 and 16/16 divide operations |
Single-cycle multiply and accumulate: |
Accumulator write back for DSP operations |
Dual data fetch |
Up to u00b116-bit shifts for up to 40-bit dataDirect Memory Access (DMA): |
8-channel hardware DMA: |
2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: |
Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) |
Most peripherals support DMAInterrupt Controller: |
5-cycle latency |
118 interrupt vectors |
Up to 67 available interrupt sources |
Up to 5 external interrupts |
7 programmable priority levels |
5 processor exceptionsDigital I/O: |
Wake-up/Interrupt-on-Change on up to 24 pins |
Output pins can drive from 3.0V to 3.6V |
All digital input pins are 5V tolerant |
4 mA sink on all I/O pinsSystem Management: |
Flexible clock options: |
External, crystal, resonator, internal RC |
Fully integrated PLL |
Extremely low jitter PLL |
Family | 16-bit DSC |
---|---|
Part Family | dsPIC33FJ128MC710A |
Part Prefix | dsPIC |
Architecture | 16 |
Core | 16-bit dsPIC DSC |
MaxSpeed (MHz) | 40 |
CPU Type | 16-bit dsPIC DSC |
CPU Speed (MIPS/DMIPS) | 40 |
Program Memory Type | Flash |
SelfWrite | Yes |
Program Memory Size (KB) | 128 |
Program Memory Size (KWords) | 42 |
Secure Bootloader (CodeGuardā¢ Security) | Advanced |
RAM (bytes) | 8192 |
Emulated EEPROM in Flash | True |
Direct Memory Access (DMA) Channels | 8 |
Temp. Range Min. | -40 |
Temp. Range Max. | 150 |
Operation Voltage Min.(V) | 3 |
Operation Voltage Max.(V) | 3.6 |
Max I/O Pins | 53 |
Pin Count | 64 |
Brown Out Reset (BOR) | BOR |
Low Voltage Detection (LVD) | None |
Power On Reset (POR) | Yes |
Internal Oscillator | 7.37 MHz, 32.768 kHz |
Number of ADCs | 1 |
ADC Channels | 16 |
Diff ADC Inputs | 4 Unipolar Differential Inputs |
Max ADC Sampling Rate (ksps) | 1100 |
Max ADC Resolution (bits) | 12 |
Max ADC Sample/Hold (S/H) | 1 |
UART | 2 |
SPIā¢ | 2 |
I2C | 2 |
Max 16 Bit Digital Timers | 9 |
Max 32 Bit Digital Timers | 4 |
Watch Dog Timers (WDT) | Yes |
Timers | 18 |
Motor Control PWM Channels | 8 |
Standalone Output Compare/ Standard PWM | 8 |
Input Capture | 8 |
Max # PWM outputs (including complementary outputs) | 16 |
Number of PWM Time Bases | 2 |
PWM Max Resolution (bits) | 16 |
PWM Resolution (time ns) | 12 |
Output Compare Channels | 8 |
USB Interface | None |
Number of CAN Modules | 1 |
Type of CAN module | CAN |
CAN Transmit Buffers | 8 |
CAN Receive Buffers | 32 |
LIN | Yes |
IrDA | Yes |
Ethernet | None |
Integrated Wireless Frequency | None |
Wireless Technology | None |
Class B Hardware | True |
Quadrature Encoder Interface (QEI) | 1 |
Parallel Port | GPIO |
JTAG | Program/Boundary Scan |
Debug Interface | ICSP |
Keydifferences | DSP, CAN, HS-PWM |
InstructionWord | 24 |
Temperature Range | -40C to +150C |
Dsc, 20Mhz, 128Kb, Qfn-Ep-64 | Newark Electronics |
Digital Signal Processors, DSP, DSC 16-bit 128KB Flash 40 MIPS | Microchip Technology Inc. DSPIC33FJ128MC506A-H/MR | RS Americas |
DSC, 20MHZ, 128KB, QFN-EP-64 | Farnell |
Where can I find additional details, specifications and documents for a DSPIC33FJ128MC506A-H/MR?
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