DSPIC33CH64MP208T-I/PT More Semiconductors - ICs by Microchip Technology

Dual Core, High Performance

Status: Active
Series: dsPIC33CH64MP208
RoHS: Compliant
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System developers designing high-end embedded control applications can benefit from a new Digital Signal Controller (DSC) with two dsPIC DSC cores in a single chip. The dsPIC33CH has one core that is designed to function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions, customized for the end application.

The dsPIC33CH is designed to facilitate independent code development for each core by separate design teams and allows seamless integration when they are brought together in one chip. The dsPIC33CH family is optimized for high-performance digital power, motor control and other high-end embedded applications requiring sophisticated algorithms.

The dsPIC33CH product family has many features that help simplify functional safety certifications for ASIL-B and ASIL-C focused applications including: 
• Functional Safety Manual, FMEDA and Diagnostic Software available under NDA upon request to your local sales office
Learn more about 16-bit Functional Safety capabilities including hardware, software, and supporting collateral

Prices starting from US$3.72


Distributor Starting From Stock
Logo for Newark Electronics Newark Electronics US$4.24
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Logo for Avnet America Avnet America US$5.12
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Logo for Microchip Technology Microchip Technology US$3.72
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Features

Operating Conditions
3V to 3.6V, -40°C to +150°C
Core: Dual 16-Bit dsPIC33CH CPUs
Master Core 90 MIPS and Slave Core 100 MIPS Operation
Independent Peripherals for Master Core and Slave Core
Configurable Shared Resources for Master Core and Slave Core
Fast 6-Cycle Divide
Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
Code Efficient (C and Assembly) Architecture
40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle, Mixed-Sign MUL Plus Hardware Divide
32-Bit Multiply Support
Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response
Zero Overhead Looping
High Performance Peripherals for Real Time Control
4 x 12-bit 3.5 MSPS ADCs
High Speed PWMs with 250ps resolution, 12 Ch
Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms
Master Core features
Core Frequency 90 MIPS @ 180 MHz
Internal Data RAM: 16 Kbytes
16-Bit Timer: 1
DMA: 6
SCCP (Capture/Compare/Timer): 8
UART: 2
SPI/I2S: 2
I2C: 2
SENT: 2
CRC: 1
QEI: 1
PTG:1
CLC: 4
16-Bit High-Speed (250ps) PWM: 4
12-bit, 3.5 Msps ADC: 1
Digital Comparator: 4
12-Bit DAC/Analog CMP Module: 1
Watchdog Timer: 1
Deadman Timer: 1
Breakpoints: 3 complex, 5 simple
Oscillator: 1
Slave Core features
Core Frequency 100 MIPS @ 200 MHz
Program Memory: 24 Kbytes (PRAM) Dual Partition with LiveUpdate
Internal Data RAM: 4 Kbytes
16-Bit Timer: 1
DMA: 2
SCCP (Capture/Compare/Timer): 4
UART: 1
SPI/I2S: 1
I2C: 1
QEI: 1
CLC: 4
16-Bit High-Speed (250ps) PWM: 8
12-bit, 3.5 Msps ADC: 3
Digital Comparator: 4
12-Bit DAC/Analog CMP Module: 3
Watchdog Timer: 1
Breakpoints: 1 complex, 2 simple
Oscillator: 1
Clock Management
Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Master Reference Clock Output
Slave Reference Clock Output
Fail-Safe Clock Monitor (FSCM)
Fast Wake-up and Start-up
Backup Internal Oscillator
LPRC Oscillator
Power Management
Low-Power Management Modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
Debugger Development Support
In-Circuit and In-Application Programming
Simultaneous Debugging Support for Master and Slave Cores
Master Only Debug and Slave Only Debug Support
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace Buffer and Run-Time Watch
Functional Safety support (ISO26262)
ASIL-B & ASIL-C focused applications
FMEDA, Diagnostic Software and Functional Safety manual available under NDA upon request to your sales office
Functional Safety hardware features
Multiple redundant clock sources
I/O Port read-back
Analog peripherals redundancies
Windowed Watchdog Timer
RAM BIST
Hardware traps
SFR locks
Write protection
Shadow working registers

Specifications

Architecture 16
MaxSpeed (MHz) 200
CPU Speed (MIPS/DMIPS) 100
Program Memory Size (KB) 64
Multiple Flash Panels False
Direct Memory Access (DMA) Channels 8
Temp. Range Min. -40
Temp. Range Max. 150
Operation Voltage Min.(V) 3
Operation Voltage Max.(V) 3.6
Pin Count 80
Low Power No
Number of Comparators 4
Number of ADCs 4
ADC Channels 23
Max ADC Resolution (bits) 12
Max ADC Sampling Rate (ksps) 3500
Number of DACs 4
DAC outputs 1
Max DAC Resolution (bits) 12
Hardware RTCC No
Motor Control PWM Channels 12
SMPS PWM Channels 12
Number of PWM Time Bases 5
Output Compare Channels 0
USB Interface None
Number of CAN Modules 0
Crypto Engine No
Quadrature Encoder Interface (QEI) 1
Segment LCD 0
LCD/Graphics Interface No
Configurable Logic Cell Modules (CLC /CCL) 8
Peripheral Pin Select (PPS)/Pin Muxing Yes
Supported in MPLAB Code Configurator Yes
Pins | Packaging 80 | TQFP
Temp Range -40C to +85C
Packing Media Tape and reel (1200)

Resources





Reference Manuals
Functional Safety Manual and FMEDA Access for dsPIC33C Family
dsPIC33/PIC24 FRM, 32-Bit Programmable CRC
dsPIC33E/PIC24E FRM, Introduction
dsPIC33E/PIC24E FRM, Data Memory
dsPIC33/PIC24 FRM, dsPIC33E/PIC24 Program Memory
dsPIC33/PIC24 FRM, Flash Programming
dsPIC33/PIC24 FRM, Interrupts
dsPIC33E/PIC24E FRM, Reset
dsPIC33E/PIC24E FRM, Watchdog Timer and Power-Saving Modes
dsPIC33/PIC24 FRM, Quadrature Encoder Interface (QEI)
dsPIC33E/PIC24E FRM, Programming and Diagnostics
dsPIC33/PIC24 FRM, Peripheral Trigger Generator (PTG)
dsPIC33/PIC24 FRM, Direct Memory Access Controller (DMA) - PIC24F FRM
dsPIC33/PIC24 FRM, Configurable Logic Cell (CLC)
dsPIC33/PIC24 FRM, Capture/Compare/PWM/Timer (MCCP and SCCP)
dsPIC33/PIC24 FRM, I2C
dsPIC33/PIC24 FRM, Serial Peripheral Interface (SPI) with Audio Codec Support
dsPIC33/PIC24 FRM, Single-Edge Nibble Transmission (SENT)
dsPIC33/PIC24 FRM, CodeGuard Intermediate Security
dsPIC33/PIC24 FRM, Deadman Timer (DMT)
dsPIC33/PIC24 FRM, 12-Bit High-Speed, Multiple SARs A/D Converter (ADC)
dsPIC33/PIC24 FRM, High-Speed Analog Comparator
dsPIC33/PIC24 FRM, Programmable Gain Amplifier (PGA)
dsPIC33/PIC24 FRM, Dual Partition Flash Program Memory
dsPIC33/PIC24 FRM, Enhanced CPU
dsPIC33/PIC24 FRM, CAN Flexible Data-Rate (FD) Protocol Module
dsPIC33/PIC24 FRM, Current Bias Generator (CBG)
dsPIC33/PIC24 FRM, High-Resolution PWM with Fine Edge Placement
dsPIC33/PIC24 FRM, IO Ports with Edge Detect
dsPIC33/PIC24 FRM, Master Slave Interface (MSI) Module
dsPIC33/PIC24 FRM, Oscillator Module with High-Speed PLL
dsPIC33/PIC24 FRM, Multiprotocol Universal Asynchronous Receiver Transmitter (UART)
dsPIC33/PIC24 FRM, Dual Watchdog Timer
dsPIC33C/PIC24 FRM, High-Speed Analog Comparator with Slope Compensation DAC
dsPIC33/PIC24 FRM, Timer1 Module



Environmental Information

JEDEC Indicator e3
ROHS Compliant
China EFUP Compliant
Device Weight (g) 0.3667
Shipping Weight (kg) 0.969167
Lead Count 80
Package Type TQFP
Package Width or Size 12x12x1mm
Soldering Composition Matte Tin

Alternative Descriptions

Dsc, 200Mhz, 64Kb, Tqfp-80 | Newark Electronics
MCU 16-Bit Dual dsPIC DSC Modified Harvard Architecture 64KB Flash 3V to 3.6V 80-Pin TQFP T/R | Avnet America
dsPIC33 100MHz Dual Core 80-Pin 64KB Flash | Microchip Technology
DSC, 200MHZ, 64KB, TQFP-80 | Farnell


Frequently Asked Questions

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The DSPIC33CH64MP208T-I/PT is listed under Semiconductors - ICs > More Semiconductors - ICs.

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Is the DSPIC33CH64MP208T-I/PT RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by Microchip Technology.

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