DSPIC33CH512MP506-I/MR More Semiconductors - ICs by Microchip Technology

100 MHz Dual-Core 16-bit DSC

Status: Active
Series: dsPIC33CH512MP506
RoHS: Compliant
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Microchipā€™s dsPIC33CH family of digital signal controllers (DSCs) feature dual 90 & 100 MIPS 16-bit dsPICĀ® DSC cores with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors. These DSCs enable the design of switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency.  These devices are also ideal for many high-performance general-purpose and robust applications.

The dsPIC33CH product family has many features that help simplify functional safety certifications for ASIL-B and ASIL-C focused applications including: 
ā€¢ Functional Safety Manual, FMEDA and Diagnostic Software available under NDA upon request to your local sales office
ā€¢ Learn more about 16-bit Functional Safety capabilities including hardware, software, and supporting collateral

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Features

Operating Conditions:
3V to 3.6V, -40Ā°C to +150Ā°C
Core: Dual 16-Bit dsPIC33CH CPUs
Master Core 90 MIPS and Slave Core 100 MIPS Operation
Independent Peripherals for Master Core and Slave Core
Configurable Shared Resources for Master Core and Slave Core
Fast 6-Cycle Divide
Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
Code Efficient (C and Assembly) Architecture
40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle, Mixed-Sign MUL Plus 6-Cycle Hardware Divide
32-Bit Multiply Support
Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response
Zero Overhead Looping
High Performance Peripherals for Real Time Control:
4 x 12-bit 3.5 MSPS ADCs: 34 Channels
High Speed PWMs with 250ps resolution, 12x2 Channels
Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms
Master Core features:
Core Frequency 90 MIPS @ 180 MHz
Program Flash: 512/256 Kbytes Dual Partition with LiveUpdate
Data RAM: 48/32 Kbytes
16-Bit Timer: 1
DMA: 6
SCCP (Capture/Compare/Timer): 8
UART: 2
SPI/I2S: 2
I2C: 2
CAN Flexible Data-Rate (FD): 2 ('50x devices only)
SENT: 2
CRC: 1
QEI: 1
PTG:1
CLC: 4
16-Bit High-Speed (250ps) PWM: 4x2
12-bit, 3.5 Msps ADC: 1, 16 Channels
Digital Comparator: 4
12-Bit DAC/Analog CMP Module: 1
Watchdog Timer: 1
Deadman Timer: 1
Breakpoints: 3 complex, 5 simple
Oscillator: 1
Slave Core features:
Core Frequency 100 MIPS @ 200 MHz
Program Memory: 72 Kbytes (PRAM) Dual Partition with LiveUpdate
Data RAM: 16 Kbytes
16-Bit Timer: 1
DMA: 2
SCCP (Capture/Compare/Timer): 4
UART: 1
SPI/I2S: 1
I2C: 1
QEI: 1
CLC: 4
16-Bit High-Speed (250ps) PWM: 8x2 Channels
12-bit, 3.5 Msps ADC: 3, 18 Channels
Digital Comparator: 4
12-Bit DAC/Analog CMP Module: 3
Watchdog Timer: 1
Deadman Timer: 1
Breakpoints: 1 complex, 2 simple
Oscillator: 1
Clock Management:
Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Master Reference Clock Output
Slave Reference Clock Output
Fail-Safe Clock Monitor (FSCM)
Fast Wake-up and Start-up
Backup Internal Oscillator
LPRC Oscillator
Power Management:
Low-Power Management Modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
Debugger Development Support
In-Circuit and In-Application Programming
Simultaneous Debugging Support for Master and Slave Cores
Master Only Debug and Slave Only Debug Support
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace Buffer and Run-Time Watch
Functional Safety support (ISO26262)
ASIL-B & ASIL-C focused applications
FMEDA, Diagnostic Software and Functional Safety manual available under NDA upon request to your sales office
Functional Safety hardware features
Multiple redundant clock sources
I/O Port read-back
Analog peripherals redundancies
Windowed Watchdog Timer
RAM BIST
Hardware traps
SFR locks
Write protection
Shadow working registers
AUTOSAR-Ready DSC supporting:
AUTOSAR (4.3.x)
ASIL B- and ASPICE-compliant MCAL drivers
ISO 26262 Functional Safety and Automotive Security

Specifications

CPU Type dsPICĀ® DSC
CPU Speed (MHz) 100
Program Memory Size (KB) 512
Multiple Flash Panels True
Direct Memory Access (DMA) Channels 6
Temp. Range Min.(CĀ°) -40
Temp. Range Max.(CĀ°) 150
Operation Voltage Min.(V) 3
Operation Voltage Max.(V) 3.6
Pin Count 64
Low Power No
Number of Comparators 4
Number of ADCs 4
ADC Channels 34
Max ADC Resolution (bits) 12
Max ADC Sampling Rate (ksps) 3500
Number of DACs 4
DAC outputs 1
Max DAC Resolution (bits) 12
Hardware RTCC No
Motor Control PWM Channels 24
SMPS PWM Channels 24
Number of PWM Time Bases 24
Output Compare Channels 12
USB Interface None
Number of CAN Modules 2
Type of CAN module CAN-FD
Crypto Engine No
Quadrature Encoder Interface (QEI) 2
Segment LCD 0
LCD/Graphics Interface No
Configurable Logic Cell Modules (CLC /CCL) 8
Peripheral Pin Select (PPS)/Pin Muxing Yes
Supported in MPLAB Code Configurator Yes
Pins | Packaging 64 | QFN
Temp Range -40C to +85C
Packing Media Tube (40)

Resources



Application Notes
AN908 - Using the dsPIC30F / dsPIC33F for Vector Control of an ACIM
AN984 - An Introduction to AC Induction Motor Control
AN1017 - Sinusoidal Control of PMSM Motors with dsPIC30F / dsPIC33F/ dsPIC33E DSC
AN3399 - Safeguarding Flash Memory Self-Write Operations
AN1078 - Dual-Shunt FOC With SMO
AN1106 - AN1106, Power Factor Correction in Power Conversion Applications
AN1114 - Switch Mode Power Supply (SMPS) Topologies (Part I)
AN1162 - Sensorless Field Oriented Control (FOC) of an AC Induction Motor (ACIM)
AN1160, Sensorless BLDC Control with Back-EMF Filtering Using a Majority Function
AN1208 - Dual-Shunt FOC With PLL and PFC
AN1206 - Sensorless Field Oriented Control (FOC) of an AC Induction Motor (ACIM) Using Field Weakening
AN1207 - Switch Mode Power Supply (SMPS) Topologies (Part II)
AN1279 - Offline UPS Reference Design Using the dsPIC DSC
AN1278 - Digital Power IPFC Reference Design Application Note
AN1292 - Dual-Shunt FOC with PLL
AN1299 - Single-Shunt Three-Phase Current Reconstruction Algorithm for Sensorless FOC of a PMSM
AN1279 - Addendum - Offline UPS Reference Design Using the dsPIC DSC
AN1338 - Grid-Connected Solar Microinverter Ref. Design Using a dsPICĀ® DSC
AN1336 - DC/DC LLC Reference Design Using the dsPICĀ® DSC - DC/DC LLC Reference Design Using the dsPICĀ® DSC
AN1335 - Phase-Shifted Full-Bridge (PSFB) Quarter Brick DC/DC Converter
AN2601 - Live Update - Online Firmware Updates in Timing-Critical Applications
AN2721 - Getting Started with Dual Core - Getting Started with Dual Core
AN1292 Source Code for MCLV-2 and MCHV-2 using dsPIC33CH512MP508




Reference Manuals
Functional Safety Manual and FMEDA Access for dsPIC33C Family
dsPIC33/PIC24 FRM, 32-Bit Programmable CRC
dsPIC33E/PIC24E FRM, Introduction
dsPIC33E/PIC24E FRM, Data Memory
dsPIC33/PIC24 Program Memory
dsPIC33/PIC24 FRM, Flash Programming
dsPIC33/PIC24 FRM, Interrupts
dsPIC33E/PIC24E FRM, Reset
dsPIC33E/PIC24E FRM, Watchdog Timer and Power-Saving Modes
dsPIC33/PIC24 FRM, Quadrature Encoder Interface (QEI)
dsPIC33E/PIC24E FRM, Programming and Diagnostics
dsPIC33/PIC24 FRM, Peripheral Trigger Generator (PTG)
dsPIC33/PIC24 FRM, Direct Memory Access Controller (DMA) - PIC24F FRM
dsPIC33/PIC24 FRM, Configurable Logic Cell (CLC)
dsPIC33/PIC24 FRM, Capture/Compare/PWM/Timer (MCCP and SCCP)
dsPIC33/PIC24 FRM, I2C
dsPIC33/PIC24 FRM, Serial Peripheral Interface (SPI) with Audio Codec Support
dsPIC33/PIC24 FRM, Single-Edge Nibble Transmission (SENT)
dsPIC33/PIC24 FRM, CodeGuard Intermediate Security
dsPIC33/PIC24 FRM, Deadman Timer (DMT)
dsPIC33/PIC24 FRM, 12-Bit High-Speed, Multiple SARs A/D Converter (ADC)
dsPIC33/PIC24 FRM, Programmable Gain Amplifier (PGA)
dsPIC33/PIC24 FRM, Dual Partition Flash Program Memory
dsPIC33/PIC24 FRM, Enhanced CPU
dsPIC33/PIC24 FRM, CAN Flexible Data-Rate (FD) Protocol Module
dsPIC33/PIC24 FRM, Current Bias Generator (CBG)
dsPIC33/PIC24 FRM, High-Resolution PWM with Fine Edge Placement
dsPIC33/PIC24 FRM, IO Ports with Edge Detect
dsPIC33/PIC24 FRM, Master Slave Interface (MSI) Module
dsPIC33/PIC24 FRM, Oscillator Module with High-Speed PLL
dsPIC33/PIC24 FRM, Multiprotocol Universal Asynchronous Receiver Transmitter (UART)
dsPIC33/PIC24 FRM, Dual Watchdog Timer
dsPIC33C/PIC24 FRM, High-Speed Analog Comparator with Slope Compensation DAC
dsPIC33/PIC24 FRM, Timer1 Module
dsPIC33/PIC24 FRM, Parallel Master Port (PMP)



Environmental Information

JEDEC Indicator e3
ROHS Compliant
China EFUP Compliant
Device Weight (g) 0.2324
Shipping Weight (kg) 0.35
Lead Count 64
Package Type QFN
Package Width or Size 9x9x0.9mm
Soldering Composition Matte Tin

Alternative Descriptions

dsPIC33 100MHz Dual Core, CAN-FD, 64-Pin, 512KB Flash | Microchip Technology
Dsc, -40 To 85Deg C, Qfn-64 | Newark Electronics
dsPIC33CH Series 64 kB RAM 584 kB Flash 16-Bit Digital Signal Controller-QFN-64 | Future Electronics
MCU 16-Bit DSPIC33 dsPIC RISC 584KB Flash 3V to 3.6V 64-Pin QFN Tube | Avnet America
DSC, -40 TO 85DEG C, QFN-64 | element14


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Yes. This part has been flagged as RoHS Compliant by Microchip Technology.

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