DSPIC33CH128MP205-I/PT Part Information
Details for DSPIC33CH128MP205-I/PT by Microchip Technology
dsPIC33CH128MP205
Part Description
System developers designing high-end embedded control applications can benefit from a new Digital Signal Controller (DSC) with two dsPIC DSC cores in a single chip. The dsPIC33CH has one core that is designed to function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions, customized for the end application. The dsPIC33CH is designed to facilitate independent code development for each core by separate design teams and allows seamless integration when they are brought together in one chip. The dsPIC33CH family is optimized for high-performance digital power, motor control and other high-end embedded applications requiring sophisticated algorithms.
Part Downloads
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Part Specifications
| Family | 16-bit DSC |
| Part Family | dsPIC33CH128MP508 |
| Part Prefix | dsPIC |
| Architecture | 16 |
| Core | 16-bit dsPIC DSC |
| MaxSpeed (MHz) | 200 |
| CPU Type | 16-bit dsPIC DSC |
| CPU Speed (MIPS/DMIPS) | 100 |
| Program Memory Type | Flash |
| SelfWrite | Yes |
| Program Memory Size (KB) | 128 |
| Program Memory Size (KWords) | 64 |
| ECC Program Flash (Error Correction Code) | True |
| Secure Bootloader (CodeGuard™ Security) | None |
| RAM (bytes) | 20480 |
| Emulated EEPROM in Flash | True |
| Direct Memory Access (DMA) Channels | 8 |
| Temp. Range Min. | -40 |
| Temp. Range Max. | 125 |
| Operation Voltage Min.(V) | 3 |
| Operation Voltage Max.(V) | 3.6 |
| Max I/O Pins | 39 |
| Pin Count | 48 |
| Brown Out Reset (BOR) | BOR |
| Low Voltage Detection (LVD) | None |
| Power On Reset (POR) | Yes |
| Internal Voltage Reference (Bandgap) | Yes |
| Internal Oscillator | 8 MHz, 32 kHz |
| Number of Comparators | 4 |
| Comparator max speed (ns) | 15 |
| Number of ADCs | 4 |
| ADC Channels | 19 |
| Diff ADC Inputs | Psuedo Differential Inputs |
| Max ADC Sampling Rate (ksps) | 3500 |
| Max ADC Resolution (bits) | 12 |
| Number of DACs | 4 |
| Max DAC Resolution (bits) | 12 |
| Programmable Gain Amp (PGA) | 3 |
| UART | 3 |
| SPI™ | 3 |
| I2C | 3 |
| I2S | 3 |
| Max 16 Bit Digital Timers | 13 |
| Max 32 Bit Digital Timers | 12 |
| Watch Dog Timers (WDT) | Yes |
| Timers | 13 |
| Stand alone PWM | 12 |
| Single output CCP (SCCP) | 12 |
| Motor Control PWM Channels | 12 |
| SMPS PWM Channels | 12 |
| Standalone Output Compare/ Standard PWM | 12 |
| Max # PWM outputs (including complementary outputs) | 24 |
| Number of PWM Time Bases | 5 |
| PWM Max Resolution (bits) | 16 |
| PWM Resolution (time ns) | 0.25 |
| USB Interface | None |
| LIN | Yes |
| IrDA | Yes |
| Ethernet | None |
| Integrated Wireless Frequency | None |
| Wireless Technology | None |
| CRC | Yes |
| Quadrature Encoder Interface (QEI) | 1 |
| CODEC Interface (I2S, AC97) | Yes |
| Configurable Logic Cell Modules (CLC /CCL) | 8 |
| Configurable Logic Cell Modules (CLC /CCL) Type | CLC |
| Peripheral Trigger Generator (PTG) | True |
| Peripheral Pin Select (PPS)/Pin Muxing | Yes |
| JTAG | Boundary Scan |
| Include in Focus Product Selector Guide | True |
| Supported in MPLAB Code Configurator | Yes |
| Temperature Range | -40C to +85C |
Alternative Part Descriptions
- 16 BIT DSC, DUAL CORE, 128K FLASH, 16K+ 4K RAM, 100MHZ, 48PIN, 48 TQFP 7X7X1MM TRAY ROHS COMPLIANT: YES | Newark Electronics
- MCU 16-Bit Dual dsPIC DSC Modified Harvard Architecture 128KB Flash 3V to 3.6V 48-Pin TQFP Tube | Avnet America
