Status: | Active |
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Series: | dsPIC33CH128MP202 |
RoHS: | Compliant |
Operating Conditions |
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3V to 3.6V, -40°C to +150°C |
Core: Dual 16-Bit dsPIC33CH CPUs |
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Master Core 90 MIPS and Slave Core 100 MIPS Operation |
Independent Peripherals for Master Core and Slave Core |
Configurable Shared Resources for Master Core and Slave Core |
Fast 6-Cycle Divide |
Message Boxes and FIFO to Communicate Between Master and Slave (MSI) |
Code Efficient (C and Assembly) Architecture |
40-Bit Wide Accumulators |
Single-Cycle (MAC/MPY) with Dual Data Fetch |
Single-Cycle, Mixed-Sign MUL Plus Hardware Divide |
32-Bit Multiply Support |
Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response |
Zero Overhead Looping |
High Performance Peripherals for Real Time Control |
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4 x 12-bit 3.5 MSPS ADCs |
High Speed PWMs with 250ps resolution, 12 Ch |
Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms |
Master Core features |
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Core Frequency 90 MIPS @ 180 MHz |
Internal Data RAM: 16 Kbytes |
16-Bit Timer: 1 |
DMA: 6 |
SCCP (Capture/Compare/Timer): 8 |
UART: 2 |
SPI/I2S: 2 |
I2C: 2 |
SENT: 2 |
CRC: 1 |
QEI: 1 |
PTG:1 |
CLC: 4 |
16-Bit High-Speed (250ps) PWM: 4 |
12-bit, 3.5 Msps ADC: 1 |
Digital Comparator: 4 |
12-Bit DAC/Analog CMP Module: 1 |
Watchdog Timer: 1 |
Deadman Timer: 1 |
Breakpoints: 3 complex, 5 simple |
Oscillator: 1 |
Slave Core features |
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Core Frequency 100 MIPS @ 200 MHz |
Program Memory: 24 Kbytes (PRAM) Dual Partition with LiveUpdate |
Internal Data RAM: 4 Kbytes |
16-Bit Timer: 1 |
DMA: 2 |
SCCP (Capture/Compare/Timer): 4 |
UART: 1 |
SPI/I2S: 1 |
I2C: 1 |
QEI: 1 |
CLC: 4 |
16-Bit High-Speed (250ps) PWM: 8 |
12-bit, 3.5 Msps ADC: 3 |
Digital Comparator: 4 |
12-Bit DAC/Analog CMP Module: 3 |
Watchdog Timer: 1 |
Breakpoints: 1 complex, 2 simple |
Oscillator: 1 |
Clock Management |
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Internal Oscillator |
Programmable PLLs and Oscillator Clock Sources |
Master Reference Clock Output |
Slave Reference Clock Output |
Fail-Safe Clock Monitor (FSCM) |
Fast Wake-up and Start-up |
Backup Internal Oscillator |
LPRC Oscillator |
Power Management |
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Low-Power Management Modes (Sleep, Idle, Doze) |
Integrated Power-on Reset and Brown-out Reset |
Debugger Development Support |
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In-Circuit and In-Application Programming |
Simultaneous Debugging Support for Master and Slave Cores |
Master Only Debug and Slave Only Debug Support |
IEEE 1149.2 Compatible (JTAG) Boundary Scan |
Trace Buffer and Run-Time Watch |
Functional Safety support (ISO26262) |
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FMEDA, Diagnostic Software and Functional Safety manual available under NDA upon request to your sales office |
ASIL-B & ASIL-C focused applications |
Functional Safety hardware features |
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Multiple redundant clock sources |
I/O Port read-back |
Analog peripherals redundancies |
Windowed Watchdog Timer |
RAM BIST |
Hardware traps |
SFR locks |
Write protection |
Shadow working registers |
Architecture | 16 |
---|---|
MaxSpeed (MHz) | 200 |
CPU Speed (MIPS/DMIPS) | 100 |
Program Memory Size (KB) | 128 |
Multiple Flash Panels | False |
Direct Memory Access (DMA) Channels | 8 |
Temp. Range Min. | -40 |
Temp. Range Max. | 150 |
Operation Voltage Min.(V) | 3 |
Operation Voltage Max.(V) | 3.6 |
Pin Count | 28 |
Low Power | No |
Number of Comparators | 4 |
Number of ADCs | 4 |
ADC Channels | 12 |
Max ADC Resolution (bits) | 12 |
Max ADC Sampling Rate (ksps) | 3500 |
Number of DACs | 4 |
DAC outputs | 1 |
Max DAC Resolution (bits) | 12 |
Hardware RTCC | No |
Motor Control PWM Channels | 12 |
SMPS PWM Channels | 12 |
Number of PWM Time Bases | 5 |
Output Compare Channels | 0 |
USB Interface | None |
Number of CAN Modules | 0 |
Crypto Engine | No |
Quadrature Encoder Interface (QEI) | 1 |
Segment LCD | 0 |
LCD/Graphics Interface | No |
Configurable Logic Cell Modules (CLC /CCL) | 8 |
Peripheral Pin Select (PPS)/Pin Muxing | Yes |
Supported in MPLAB Code Configurator | Yes |
Pins | Packaging | 28 | UQFN |
Temp Range | -40C to +85C |
Packing Media | Tube (61) |
Data Sheets |
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dsPIC33CH128MP508 Family Datasheet |
Programming Specifications |
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16-Bit MCU and DSC Programmer's Reference Manual |
dsPIC33CH128MP508 Family Flash Programming Specification |
dsPIC33C Family Flash Program Exec |
JEDEC Indicator | e3 |
---|---|
ROHS | Compliant |
China EFUP | Compliant |
Device Weight (g) | 0.0035 |
Shipping Weight (kg) | 0.114754 |
Lead Count | 28 |
Package Type | UQFN |
Package Width or Size | 6x6x0.55mm |
Soldering Composition | Matte Tin |
dsPIC33 100MHz Dual Core 28-Pin 128KB Flash | Microchip Technology |
Dsc, 200Mhz, 128Kb, Uqfn-Ep-28 | Newark Electronics |
MCU 16-Bit Dual dsPIC DSC Modified Harvard Architecture 128KB Flash 3V to 3.6V 28-Pin UQFN Tube | Avnet America |
DSC, 200MHZ, 128KB, UQFN-EP-28 | Farnell |
Where can I find additional details, specifications and documents for a DSPIC33CH128MP202-I/2N?
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Is the DSPIC33CH128MP202-I/2N RoHS compliant?
Yes. This part has been flagged as RoHS Compliant by Microchip Technology.
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