Options for Price Comparison
Distributor Statistics for SY89874UMG
Total in Stock: -
Lowest MOQ: -
Average Price: - per unit
Stocking Distributors: -
Loading...
Loading Results for SY89874UMG
Details for SY89874UMG by Microchip Technology
SY89874U
SY89874UMG
Buy Directly from Microchip Technology Inc (1715 in stock) $6.2500
2.5V/3.3V PECL Output Clock Divider/Fanout
SY89874UMG image

SY89874UMG by Microchip Technology

2.5V/3.3V PECL Output Clock Divider/Fanout
Features
Integrated programmable clock divider and 1:2 fanout buffer
Guaranteed AC performance over temperature and voltage:
>2.5GHz fMAX
<250ps tr/tf
<15ps within device skew
Low jitter design:
<10psPP total jitter
<1psRMS cycle-to-cycle jitter
Unique input termination and VTpin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL
TTL/CMOS inputs for select and reset
100k EP compatible LVPECL outputs
Parallel programming capability
Programmable divider ratios of 1, 2, 4, 8 and 16
Low voltage operation 2.5V or 3.3V
Output disable function
-40°C to 85°C temperature range
Available in 16-pin (3mm x 3mm) MLF® package
Description

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked, lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N).

Specifications
Sub Group:
Divider
Product Type:
Divider
Input:
ANY
Output:
LVPECL
Supply Voltage:
2.5/3.3V
Max Freq (GHz):
2.5
Max Prop Delay (ps):
790
Icc (mA):
50
Max Within Device Skew (ps):
<15
OE:
True
Temperature Range:
-40C to +85C
Alternate Descriptions
2.5V/3.3V PECL Output Clock Onlinecomponents.com
CLOCK DIVIDER/FANOUT BUFFER, 2.5GHZ, QFN; Clock IC Type:Clock Divider, Fanout Buffer; Frequency:2.5GHz; No. of Outputs:2Outputs; Supply Voltage Min:2.375V; Supply Voltage Max:3.63V; Clock IC Case Style:QFN; No. of Pins:16Pins; RoHS Compliant: Yes Newark Electronics
Clock Buffer 2-OUT 16-Pin QFN Tube Avnet America
2.5V/3.3V PECL Output Clock Divider/Fanout Microchip Technology Inc
SY89874U-2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/ Fanout Buffer Future Electronics
Similar Part
Details for SY89874UMG by Microchip Technology
SY89874U
SY89874UMG
Buy Directly from Microchip Technology Inc (1715 in stock) $6.2500
CLOCK DIVIDER/FANOUT BUFFER 2.5GHZ QFN
SY89874UMG image

SY89874UMG by Microchip Technology

CLOCK DIVIDER/FANOUT BUFFER 2.5GHZ QFN
Features
100k EP-compatible LVPECL outputs
<10psPP total jitter
<15ps within-device skew
<1psRMS cycle-to-cycle jitter
<250ps tr/tf
>2.5GHz fMAX
Guaranteed AC performance over temperature and voltage:
Low-jitter design:
Low-voltage operation 2.5V or 3.3V
Output disable function
Parallel programming capability
Programmable divider ratios of 1, 2, 4, 8 and 16
TTL/CMOS inputs for select and reset
Unique input termination and VT pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS, and HSTL
u201340u00b0C to 85u00b0C te
Part Information
SY89874UMG image
RoHS Compliant
Description
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass- through. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N).
Specifications
Clock IC Type:
Clock Divider Fanout Buffer
Frequency:
2.5GHz
No. of Outputs:
2Outputs
Supply Voltage Min:
2.375V
Supply Voltage Max:
3.63V
Clock IC Case Style:
QFN
No. of Pins:
16Pins
Operating Temperature Min:
-40°C
Operating Temperature Max:
85°C
Product Range:
-
Automotive Qualification Standard:
-
RoHS Phthalates Compliant:
Yes
MSL:
MSL 3 - 168 hours
SVHC:
No SVHC (27-Jun-2018)
Alternate Descriptions
2.5V/3.3V PECL Output Clock Onlinecomponents.com
CLOCK DIVIDER/FANOUT BUFFER, 2.5GHZ, QFN; Clock IC Type:Clock Divider, Fanout Buffer; Frequency:2.5GHz; No. of Outputs:2Outputs; Supply Voltage Min:2.375V; Supply Voltage Max:3.63V; Clock IC Case Style:QFN; No. of Pins:16Pins; RoHS Compliant: Yes Newark Electronics
Clock Buffer 2-OUT 16-Pin QFN Tube Avnet America
2.5V/3.3V PECL Output Clock Divider/Fanout Microchip Technology Inc
SY89874U-2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/ Fanout Buffer Future Electronics