SY89874UMG

Semiconductors - ICs

> Clock Timing & Frequency Management

> Clock Synthesizers & Generators

Organise Price Comparison Results by
distributor space
Distributor Statistics for SY89874UMG
Total in Stock: -in-stock
Lowest MOQ: -
SELECT OPTIONS
Lowest price for your selection
-
in Stock
-
Average Price: - per unit
Stocking Distributors: -
Price Comparison for SY89874UMG
Details for Microchip Technology

SY89874UMG

2.5V/3.3V PECL Output Clock Divider/Fanout
Buy Directly from Microchip Technology (7115 in Stock)
$3.9500 per unit
Series Information for SY89874UMG - Microchip Technology

Features

  • feature
    100k EP-compatible LVPECL outputs
  • feature
    <10psPP total jitter
  • feature
    <15ps within-device skew
  • feature
    <1psRMS cycle-to-cycle jitter
  • feature
    <250ps tr/tf
  • feature
    >2.5GHz fMAX
  • feature
    Guaranteed AC performance over temperature and voltage:
  • feature
    Low-jitter design:
  • feature
    Low-voltage operation 2.5V or 3.3V
  • feature
    Output disable function
  • feature
    Parallel programming capability
  • feature
    Programmable divider ratios of 1, 2, 4, 8 and 16
  • feature
    TTL/CMOS inputs for select and reset
  • feature
    Unique input termination and VT pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS, and HSTL
  • feature
    u201340u00b0C to 85u00b0C te

Description

CLOCK DIVIDER/FANOUT BUFFER 2.5GHZ QFN
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass- through. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N).

Specifications

Clock IC Type:
Clock Divider Fanout Buffer
Frequency:
2.5GHz
No. of Outputs:
2Outputs
Supply Voltage Min:
2.375V
Supply Voltage Max:
3.63V
Clock IC Case Style:
QFN
No. of Pins:
16Pins
Operating Temperature Min:
-40°C
Operating Temperature Max:
85°C
Product Range:
-
Automotive Qualification Standard:
-
RoHS Phthalates Compliant:
Yes
MSL:
MSL 3 - 168 hours
SVHC:
No SVHC (27-Jun-2018)

Alternate Descriptions

Avnet America

Clock Buffer 2-OUT 16-Pin QFN Tube

Avnet America product

Microchip Technology Inc

2.5V/3.3V PECL Output Clock Divider/Fanout

Future Electronics

SY89874U-2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/ Fanout Buffer