SY89873LMG More Semiconductors - ICs by Microchip Technology

Status: Active
Series: SY89873L
RoHS: Compliant
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This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89873L includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to all AC- or DC-coupled differential logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89873L is part of Micrel's high-speed Precision Edge® timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an LVPECL output, consider the SY89871U.The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing Diagram.

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Prices starting from US$2.19

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Features

>2.0GHz fMAX output toggle
>3.0GHz fMAX input
<800ps tPD (matched-delay between banks)
<15ps within-device skew
<190ps rise/fall time
<1psRMS cycle-to-cycle jitter
Unique input termination and VTpin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
Precision differential LVDS outputs
Matched delay: all outputs have matched delay, independent of divider setting
TTL/CMOS inputs for select and reset/disable
Bank A: Buffered copy of input clock (undivided)
Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies
3.3V power supply
Wide operating temperature range: -40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package

Specifications

Product Type Divider
Description 2 Banks (÷1, ÷2, ÷4, ÷8, ÷16); 2 Outputs
Input ANY
Output LVDS
Supply Voltage 3.3V
Max Freq (GHz) 2
Max Data (Gbps) 0
Max Prop Delay (ps) 800
Icc (mA) 85
Power Supply 0
Max Within Device Skew (ps) 15
OE True
RPE False
FSI False
Input Mux False
Input EQ False
Delay Resolution ps/step 0
Output Type LVDS
Number Of Outputs 0
Pins | Packaging 16 | VQFN
Temp Range -40C to +85C
Packing Media Tube (100)

Environmental Information

JEDEC Indicator e4
ROHS Compliant
China EFUP Compliant
Device Weight (g) 0.0213
Shipping Weight (kg) 0.05
Lead Count 16
Package Type VQFN
Package Width or Size 3x3x1.00mm
Soldering Composition NiPdAu

Alternative Descriptions

3.3V LVDS Output Clock Divider/Fanout | Microchip Technology
SY89873U - 2 GHz Any Diff. In-to-LVDS Programmable Clock Divider/ Fanout Buffer | Future Electronics
Clk Divider/Fan-Out Buffer, 2Ghz, Qfn-16 |Microchip SY89873LMG | Newark Electronics
MCCSY89873LMG | Avnet America
CLK DIVIDER/FAN-OUT BUFFER, 2GHZ, QFN-16 | Farnell


Frequently Asked Questions

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What category does SY89873LMG fall under?

The SY89873LMG is listed under Semiconductors - ICs > More Semiconductors - ICs.

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Is the SY89873LMG RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by Microchip Technology.

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