SY89871UMG

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Details for Microchip Technology

SY89871UMG

2.5V/3.3V PECL Output Clock Divider/Fanout
Buy Directly from Microchip Technology (5575 in Stock)
$5.0800 per unit
Series Information for SY89871UMG - Microchip Technology

Features

  • feature
    100K EP compatible LVPECL outputs
  • feature
    231fs RMS phase jitter (Typ)
  • feature
    <15ps within-device skew
  • feature
    <250ps tr/tf
  • feature
    <670ps tpd (matched delay)
  • feature
    >2.5GHz fMAX
  • feature
    Available in 16
  • feature
    Bank A: undivided pass-through (QA)
  • feature
    Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
  • feature
    Guaranteed AC performance:
  • feature
    Low jitter design
  • feature
    Matched delay: all outputs have matched delay, independent of divider setting
  • feature
    Parallel programming capability
  • feature
    Power supply 3.3V or 2.5V
  • feature
    TTL/CMOS inputs for select and reset
  • feature
    Unique patent-pending input termination and VT pin for DC- and AC- coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
  • feature
    Wide operating temperature range: -40u00b0C to +85u00b0C

Description

CLK DIVIDER/FAN-OUT BUFFER 2.5GHZ QFN
The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency- locked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8, and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting.

Specifications

Clock IC Type:
Clock Divider Fanout Buffer
Frequency:
2.5GHz
No. of Outputs:
3Outputs
Supply Voltage Min:
2.37V
Supply Voltage Max:
3.6V
Clock IC Case Style:
QFN
No. of Pins:
16Pins
Operating Temperature Min:
-40°C
Operating Temperature Max:
85°C
Product Range:
-
Automotive Qualification Standard:
-
RoHS Phthalates Compliant:
Yes
MSL:
MSL 1 - Unlimited
SVHC:
No SVHC (27-Jun-2018)

Alternate Descriptions

Avnet America

Clock Buffer 3-OUT 16-Pin QFN Tube

Avnet America product

Microchip Technology Inc

2.5V/3.3V PECL Output Clock Divider/Fanout

Future Electronics

SY89871U-2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/ Fanout Buffer