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Details for SY89871UMG by Microchip Technology
SY89871UMG
SY89871UMG
Buy Directly from Microchip Technology Inc (2680 in stock) $8.0500
2.5V/3.3V PECL Output Clock Divider/Fanout
SY89871UMG image

SY89871UMG by Microchip Technology

2.5V/3.3V PECL Output Clock Divider/Fanout
Features
Two matched-delay outputs:
Bank A: undivided pass-through (QA)
Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
Matched delay: all outputs have matched delay, independent of divider setting
Guaranteed AC performance:
>2.5GHz fMAX
<250ps tr/tf
<670ps tpd (matched delay)
<15ps within-device skew
Low jitter design
231fsRMS phase jitter (typ.)
Power supply 3.3V or 2.5V
Unique patent-pending input termination and VT pin for DC- and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
TTL/CMOS inputs for select and reset
100K EP compatible LVPECL outputs
Parallel programming capability
Wide operating temperature range: -40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package
Description
The SY89871UMG is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency locked lower speed version of the input clock (Bank B).Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting.
Specifications
Sub Group:
Divider
Product Type:
Divider
Supply Voltage:
2.3 to 3.6V
Output Type:
LVPECL
Temperature Range:
-40C to +85C
Alternate Descriptions
2.5V/3.3V PECL Output Clock Onlinecomponents.com
CLK DIVIDER/FAN-OUT BUFFER, 2.5GHZ, QFN; Clock IC Type:Clock Divider, Fanout Buffer; Frequency:2.5GHz; No. of Outputs:3Outputs; Supply Voltage Min:2.37V; Supply Voltage Max:3.6V; Clock IC Case Style:QFN; No. of Pins:16Pins; OperatingRoHS Compliant: Yes Newark Electronics
Clock Buffer 3-OUT 16-Pin QFN Tube Avnet America
2.5V/3.3V PECL Output Clock Divider/Fanout Microchip Technology Inc
SY89871U-2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/ Fanout Buffer Future Electronics
Details for SY89871UMG by Microchip Technology
SY89871UMG
SY89871UMG
Buy Directly from Microchip Technology Inc (2680 in stock) $8.0500
CLK DIVIDER/FAN-OUT BUFFER 2.5GHZ QFN
SY89871UMG image

SY89871UMG by Microchip Technology

CLK DIVIDER/FAN-OUT BUFFER 2.5GHZ QFN
Features
100K EP compatible LVPECL outputs
231fs RMS phase jitter (Typ)
<15ps within-device skew
<250ps tr/tf
<670ps tpd (matched delay)
>2.5GHz fMAX
Available in 16
Bank A: undivided pass-through (QA)
Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
Guaranteed AC performance:
Low jitter design
Matched delay: all outputs have matched delay, independent of divider setting
Parallel programming capability
Power supply 3.3V or 2.5V
TTL/CMOS inputs for select and reset
Unique patent-pending input termination and VT pin for DC- and AC- coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
Wide operating temperature range: -40u00b0C to +85u00b0C
Part Information
SY89871UMG image
RoHS Compliant
Description
The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency- locked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8, and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting.
Specifications
Clock IC Type:
Clock Divider Fanout Buffer
Frequency:
2.5GHz
No. of Outputs:
3Outputs
Supply Voltage Min:
2.37V
Supply Voltage Max:
3.6V
Clock IC Case Style:
QFN
No. of Pins:
16Pins
Operating Temperature Min:
-40°C
Operating Temperature Max:
85°C
Product Range:
-
Automotive Qualification Standard:
-
RoHS Phthalates Compliant:
Yes
MSL:
MSL 1 - Unlimited
SVHC:
No SVHC (27-Jun-2018)
Alternate Descriptions
2.5V/3.3V PECL Output Clock Onlinecomponents.com
CLK DIVIDER/FAN-OUT BUFFER, 2.5GHZ, QFN; Clock IC Type:Clock Divider, Fanout Buffer; Frequency:2.5GHz; No. of Outputs:3Outputs; Supply Voltage Min:2.37V; Supply Voltage Max:3.6V; Clock IC Case Style:QFN; No. of Pins:16Pins; OperatingRoHS Compliant: Yes Newark Electronics
Clock Buffer 3-OUT 16-Pin QFN Tube Avnet America
2.5V/3.3V PECL Output Clock Divider/Fanout Microchip Technology Inc
SY89871U-2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/ Fanout Buffer Future Electronics