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Details for SY100EL14VZG by Microchip Technology
SY100EL14V
SY100EL14VZG
Buy Directly from Microchip Technology Inc (4598 in stock) $2.5300
3.3V/5V 1:5 Clock Distribution
SY100EL14VZG image

SY100EL14VZG by Microchip Technology

3.3V/5V 1:5 Clock Distribution
Features
3.3V and 5V power supply options
70fsRMS typical additive phase jitter
Typical 30ps output-to-output skew
Max. 50ps output-to-output skew
Synchronous enable/disable
Multiplexed clock input
75KΩ internal input pull-down resistors
Available in 20-pin SOIC package
Description
The SY100EL14V is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The EL14V is suitable for operation in systems operating from 3.3V to 5.0V supplies. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor.

The VBBoutput is designed to act as the switching reference for the input of the EL14V under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.The EL14V features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control.The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2.
Specifications
Sub Group:
Fanout
Product Type:
Fanout & Buffer and Drivers
Input:
PECL
Output:
PECL
Supply Voltage:
3.3/5V
Max Freq (GHz):
0.75
Max Prop Delay (ps):
<880
Icc (mA):
32
Max Within Device Skew (ps):
<50
OE:
True
Input Mux:
True
Temperature Range:
-40C to +85C
Alternate Descriptions
3.3V/5V 1:5 CLOCK DISTRIBUTION 20 SOIC .300IN TUBE Newark Electronics
3.3V/5V 1:5 CLOCK DISTRIBUTION Avnet America
3.3V/5V 1:5 Clock Distribution Microchip Technology Inc
SY100EL14V Series 5 / 3.3 V SMT 1:5 Clock Distribution Chip - SOIC-20 Future Electronics
Details for SY100EL14VZG by Microchip Technology
SY100EL14V
SY100EL14VZG
Buy Directly from Microchip Technology Inc (4598 in stock) $2.5300
CLOCK DISTRIBUTION 750MHZ NSOIC-20
SY100EL14VZG image

SY100EL14VZG by Microchip Technology

CLOCK DISTRIBUTION 750MHZ NSOIC-20
Features
70fsRMS typical additive phase jitter
75ku2126 internal input pull-down resistors
Max. 50ps output-to-output skew
Multiplexed clock input
Synchronous enable/disable
Typical 30ps output-to-output skew
Part Information
SY100EL14VZG image
RoHS Compliant
Description
The SY100EL14V is a low-skew, 1:5 clock distribution chip designed explicitly for low-skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The EL14V is suitable for operation in systems operating with 3.3V to 5.0V supplies. If a single-ended input is to be used, the VBB output should be connected to the /CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL14V under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The EL14V features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL pin will select the differential clock input. The common enable (/EN) is synchronous, so that the outputs will only be enabled/disable when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock. Therefore, all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and /CLK input will bias around VCC/2.
Specifications
Clock IC Type:
Clock Distribution
Frequency:
750MHz
No. of Outputs:
5Outputs
Supply Voltage Min:
-3V
Supply Voltage Max:
5V
Clock IC Case Style:
WSOIC
No. of Pins:
20Pins
Operating Temperature Min:
-40°C
Operating Temperature Max:
85°C
Product Range:
-
Automotive Qualification Standard:
-
RoHS Phthalates Compliant:
Yes
MSL:
MSL 1 - Unlimited
SVHC:
No SVHC (15-Jan-2018)
Alternate Descriptions
3.3V/5V 1:5 CLOCK DISTRIBUTION 20 SOIC .300IN TUBE Newark Electronics
3.3V/5V 1:5 CLOCK DISTRIBUTION Avnet America
3.3V/5V 1:5 Clock Distribution Microchip Technology Inc
SY100EL14V Series 5 / 3.3 V SMT 1:5 Clock Distribution Chip - SOIC-20 Future Electronics