SN65LVDS104D

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Details for Texas Instruments

SN65LVDS104D

1:4 LVDS Clock Fanout Buffer
Buy Directly from Texas Instruments (5539 in Stock)
$2.6100 per unit
Series Information for SN65LVDS104D - Texas Instruments

Features

  • feature
    Bus-Pin ESD Protection Exceeds 16 kV
  • feature
    Driver Outputs Are High-Impedance When Disabled or With VCC <1.5 V
  • feature
    Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Networks
  • feature
    LVTTL Levels Are 5-V Tolerant
  • feature
    Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-u2126 Load
  • feature
    Operates From a Single 3.3-V Supply
  • feature
    Propagation Delay Time u2013 SN65LVDS105 u2013 2.2 ns (Typ) u2013 SN65LVDS104 u2013 3.1 ns (Typ)
  • feature
    Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard u2013 SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels u2013 SN65LVDS104 Receives Differential Input Levels, u00b1100 mV
  • feature
    SOIC and TSSOP Packaging
  • feature
    Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz

Description

IC CLOCK BUFFER LVDS SMD SOIC16
The SN65LVDS10x are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.) The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream. The SN65LVDS10x are characterized for operation from –40°C to 85°C. The SN65LVDS10x are members of a family of LVDS repeaters. A brief overview of the family is provided in the Selection Guide to LVDS Repeaters section.

Specifications

Device Type:
Differential Line Receiver
Peak-to-Peak Jitter Max:
147ps
Supply Current Max:
35mA
Operating Temperature Min:
-40°C
Operating Temperature Max:
85°C
Supply Voltage Min:
3V
Supply Voltage Max:
3.6V
Driver Case Style:
SOIC
No. of Pins:
16Pins
Signaling Rate:
400Mbps
Signal Input Type:
LVDS
Output Level Type:
LVDS
ESD HBM:
16kV
Product Range:
-
Automotive Qualification Standard:
-
RoHS Phthalates Compliant:
Yes
MSL:
MSL 1 - Unlimited
SVHC:
No SVHC (27-Jun-2018)
Frequency:
400MHz
Input Current:
-20µA
Input Type:
LVDS
No. of Outputs:
4Outputs
Operating Temperature Range:
-40°C to +85°C
Supply Voltage Range:
3V to 3.6V
Termination Type:
Surface Mount Device
Type:
Repeater

Alternate Descriptions

Avnet America

LVDS Receiver 0.454V 16-Pin SOIC Tube

Avnet Europe

LVDS Receiver 0.454V 16-Pin SOIC Tube

Texas Instruments

1:4 LVDS Clock Fanout Buffer

Texas Instruments product