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Details for SN65DSI83TPAPRQ1 by Texas Instruments
Electronic & Electrical Components > Semiconductors - ICs > Driver & Interface ICs
DSI TO LVDS BRIDGE AEC-Q100 HTQFP-64
SN65DSI83TPAPRQ1 image

SN65DSI83TPAPRQ1 by Texas Instruments

DSI TO LVDS BRIDGE AEC-Q100 HTQFP-64
Features
1.8-V Main VCC Power Supply
AEC-Q100 Qualified With the Following Results: u2013 Device Temperature Grade 2: u201340u00b0C to +105u00b0C Ambient Operating Temperature u2013 Device HBM ESD Classification Level 3A u2013 Device CDM ESD Classification Level C6
Implements MIPIu00ae D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
LVDS Output Clock Range of 25 MHz to 154 MHz
LVDS Pixel Clock May be Sourced from Free- Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
Maximum Resolution up to 60 fps WUXGA 1920 u00d7 1200 at 18 bpp and 24 bpp Color With Reduced Blanking. Suitable for 60 fps 1366 u00d7 768 / 1280 u00d7 800 at 18 bpp and 24 bpp
Output for Single-Link LVDS
Packaged in 64-pin 10-mm u00d7 10-mm HTQFP
Qualified for Automotive Applications
Single-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
Supports Single Channel DSI to Single-Link LVDS Operating Mode
Part Information
SN65DSI83TPAPRQ1 image
RoHS Compliant
Description
The SN65DSI83-Q1 DSI-to-LVDS bridge features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link. The SN65DSI83-Q1 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83-Q1 device is also suitable for applications using 60 fps 1366 × 768/1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces. The SN65DSI83-Q1 device is implemented in a small outline 10-mm × 10-mm HTQFP package with a 0.5-mm pitch, and operates across a temperature range from –40°C to +105°C.
Specifications
Bridge Type:
DSI to LVDS
Supply Voltage Min:
1.65V
Supply Voltage Max:
1.95V
Interface Case Style:
HTQFP
No. of Pins:
64Pins
Operating Temperature Min:
-40°C
Operating Temperature Max:
105°C
Product Range:
-
Automotive Qualification Standard:
AEC-Q100
RoHS Phthalates Compliant:
Yes
MSL:
MSL 3 - 168 hours
SVHC:
No SVHC (27-Jun-2018)
Alternate Descriptions
DSI TO LVDS BRIDGE, AEC-Q100, HTQFP-64; Bridge Type:DSI to LVDS; Supply Voltage Min:1.65V; Supply Voltage Max:1.95V; Interface Case Style:HTQFP; No. of Pins:64Pins; Operating Temperature Min:-40°C; Operating Temperature Max:105°C; RoHS Compliant: Yes Newark Electronics
LVDS Serializer 0.535V 64-Pin HTQFP T/R Avnet America
LVDS Serializer 0.535V 64-Pin HTQFP T/R Avnet Europe