Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and Parity) to or
From the Serial Data.
After Reset, All Registers Are Identical to the
16450 Register Set.
Capable of Running All Existing 16450 Software.
Complete Status Reporting Capabilities.
False Start Bit Detection.
Full Prioritized Interrupt System Controls.
Fully Programmable Serial-Interface
u2013 5-, 6-, 7-, or 8-Bit Characters
u2013 Even, Odd, or No-Parity Bit Generation and
u2013 1-, 1 1/2-, or 2-Stop Bit Generation
u2013 Baud Generation (DC to 1.5 M Baud).
Holding and Shift Registers in the 16450 Mode
Eliminate the Need for Precise Synchronization
Between the CPU and Serial Data.
In the FIFO(1)
Mode Transmitter and Receiver Are
Each Buffered With 16 Byte FIFOu2019s to Reduce the
Number of Interrupts Presented to the CPU.
Independent Receiver Clock Input.
Independently Controlled Transmit, Receive, Line
Status, and Data Set Interrupts.
Internal Diagnostic Capabilities
u2013 Loopback Controls for Communications Link
u2013 Break, Parity, Overrun, Framing Error
Line Break Generation and Detection.
MODEM Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD).
Pin for Pin Compatible With the Existing 16450
Except for CSOUT (24) and NC (29). The Former
CSOUT and NC Pins Are TXRDY and RXRDY,
Programmable Baud Generator Divides Any Input
Clock by 1 to (216
u2013 1) and Generates the 16 u00d7
TRI-STATE TTL Drive for the Data and Control