MC100EP14DTG Clock & Data Distribution by ON Semiconductor

Clock Driver, 1:5 Differential, ECL / HSTL, 3.3 V / 5.0 V

Status: Active
Series: MC100EP14
RoHS: Compliant
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The MC100EP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions. The EP14 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The common enable (ENbar) is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is locked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

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Prices starting from US$6.00

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Features

400 ps Typical Propagation Delay
100 ps Device-to-Device Skew
25 ps Within Device Skew
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State

Specifications

Description MC100EP14
Compliance Pb-free Halide free
Type Buffer
Channels 1
Input / Output Ratio 2:1:5
Input Level CML ECL HSTL LVDS
Output Level ECL
VCC Typ (V) 3.3 5
tJitterRMS Typ (ps) 0.2
tskew(o-o) Max (ps) 35
tpd Typ (ns) 0.375
tR & tF Max (ps) 205
fmaxClock Typ (MHz) 2000
Package Type TSSOP-20

Alternative Descriptions

Bbg Ecl 1:5 Clock Distrib Rohs Compliant: Yes |Onsemi MC100EP14DTG. | Newark Electronics
MC100EP14 Series 2GHz 5.5V 1:5 Differential ECL/PECL/HSTL Clock Driver-TSSOP-20 | Future Electronics
Clock Driver 2-IN ECL/PECL 20-Pin TSSOP Rail | Avnet America
MC100EP14DTG, Clock Driver ECL, LEVP ECL, PECL 2-Input, 20-Pin TSSOP | ON Semiconductor MC100EP14DTG | RS Americas
IC, SM, LOGIC, ECL, CLOCK GEN | element14


Frequently Asked Questions

Where can I find additional details, specifications and documents for a MC100EP14DTG?

Additional datasheets, footprints and schematics for MC100EP14DTG are listed on our Part Details page. You can also find images and similar parts to MC100EP14DTG on this page.

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What category does MC100EP14DTG fall under?

The MC100EP14DTG is listed under Timing, Logic & Memory > Clock & Data Distribution > Drivers & Fanout Buffers.

Can I view similar or alternative parts?

You can view similar parts to MC100EP14DTG when available in the Drivers & Fanout Buffers range under the specifications section at the bottom of the details page.

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Is the MC100EP14DTG RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by ON Semiconductor.

Which authorised distributors for MC100EP14DTG have stock available?

Authorised distributors including Newark Electronics, Future Electronics, Avnet America, RS Americas and element14 have stock available or on a lead time for MC100EP14DTG.

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