MC100EL34DG Clock & Data Distribution by ON Semiconductor

5.0 V ECL ÷2, ÷4, ÷8 Clock Generation Chip

Status: Active
Series: MC100EL34
RoHS: Compliant
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The MC10/100EL34 is a low skew divide by 2, divide by 4, divide by 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The VBB output is designed to act as the switching reference for the input of the EL34 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system. The 100 Series contains temperature compensation.

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Features

50ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
Internal Input Pulldown Resistors on CLK(s), ENbar, and MR
Pb-Free Packages are Available

Specifications

Description MC100EL34
Compliance Pb-free Halide free
Type Divider
Input Level ECL
Output Level ECL
VCC Typ (V) 5
fMax Typ (MHz) 1100
tpd Typ (ns) 1080
tR & tF Max (ps) 475
Package Type SOIC-16

Alternative Descriptions

Clock Generator Chip, So-16 | Newark Electronics
Clock Generator 16-Pin SOIC Rail | Avnet America


Frequently Asked Questions

Where can I find additional details, specifications and documents for a MC100EL34DG?

Additional datasheets, footprints and schematics for MC100EL34DG are listed on our Part Details page. You can also find images and similar parts to MC100EL34DG on this page.

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What category does MC100EL34DG fall under?

The MC100EL34DG is listed under Timing, Logic & Memory > Clock & Data Distribution > Arithmetic Functions.

Can I view similar or alternative parts?

You can view similar parts to MC100EL34DG when available in the Arithmetic Functions range under the specifications section at the bottom of the details page.

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Is the MC100EL34DG RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by ON Semiconductor.

Which authorised distributors for MC100EL34DG have stock available?

Authorised distributors including Newark Electronics and Avnet America have stock available or on a lead time for MC100EL34DG.

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