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Details for LMK04208NKDT by Texas Instruments
Semiconductors - ICs > Clock Timing & Frequency Management > Clock Synthesizers & Generators
CLOCK JITTER CLEANER 3.072GHZ WQFN-64
LMK04208NKDT image

LMK04208NKDT by Texas Instruments

CLOCK JITTER CLEANER 3.072GHZ WQFN-64
Features
0-Delay Mode
25 ps Step Analog Delay Control
3.15-V to 3.45-V Operation
50 % Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
6 LVPECL, LVDS, or LVCMOS Programmable Outputs
64-Pin WQFN Package (9.0 u00d7 9.0 u00d7 0.8 mm)
7 Differential Outputs, Up to 14 Single-Ended u2013 Up to 6 VCXO/Crystal Buffered Outputs
Clock Rates of Up to 1536 MHz
Digital Delay: Fixed or Dynamically Adjustable
Dual Loop PLLatinumu2122 PLL Architecture
Industrial Temperature Range: u201340u00b0C to +85u00b0C
Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
PLL1 u2013 Integrated Low-Noise Crystal Oscillator Circuit u2013 Holdover Mode when Input Clocks are Lost u2013 Automatic or Manual Triggering/Recovery
PLL2 u2013 Normalized PLL Noise Floor of u2013227 dBc/Hz u2013 Phase Detector Rate of Up to 155 MHz u2013 OSCin Frequency-Doubler u2013 Integrated Low-Noise VCO or External VCO Mode
Three Default Clock Outputs at Power Up
Two Redundant Input Clocks with LOS u2013 Automatic and Manual Switch-Over Modes
Ultra-Low RMS Jitter Performance u2013 111 fs, RMS Jitter (12 kHz to 20 MHz) u2013 123 fs, RMS Jitter (100 Hz to 20 MHz)
Part Information
LMK04208NKDT image
RoHS Compliant
Description
The LMK04208 is a high performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture is capable of 111 fs, RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode. The dual loop architecture consists of two highperformance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the farout phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
Specifications
Clock IC Type:
Jitter Cleaner
Frequency:
3.072GHz
No. of Outputs:
7Outputs
Supply Voltage Min:
3.15V
Supply Voltage Max:
3.45V
Clock IC Case Style:
WQFN
No. of Pins:
64Pins
Operating Temperature Min:
-40°C
Operating Temperature Max:
85°C
Product Range:
-
Automotive Qualification Standard:
-
RoHS Phthalates Compliant:
Yes
MSL:
MSL 3 - 168 hours
SVHC:
No SVHC (27-Jun-2018)
Alternate Descriptions
Clock Jitter Cleaner 64-Pin WQFN T/R Avnet America
Clock Jitter Cleaner 64-Pin WQFN T/R Avnet Europe