The DS90UR90xQ-Q1 chipset translates a parallel RGB video interface into a high-speed serialized interface over a single pair. This serial bus scheme makes system design easy by eliminating skew problems between clock and data, reducing the number of connector pins, reducing the interconnect size, weight, cost, and easing overall PCB layout. In addition, internal DC-balanced decoding is used to support AC-coupled interconnects. The DS90UR905Q-Q1 serializer embeds the clock, balances the data payload, and level shifts the signals to high-speed, low voltage differential signaling. Up to 24 inputs are serialized, along with the three video control signals. This supports full 24-bit color or 18-bit color and 6 general-purpose signals (for example, Audio I2S applications). The DS90UR906Q-Q1 deserializer recovers the data (RGB) and control signals and extracts the clock from the serial stream. The DS90UR906Q-Q1 is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.