DS90CR286ATDGGRQ1

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Details for Texas Instruments

DS90CR286ATDGGRQ1

3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Chan Link 66 MHz
Buy Directly from Texas Instruments (5950 in Stock)
$5.2000 per unit
Series Information for DS90CR286ATDGGRQ1 - Texas Instruments

Features

  • feature
    20 to 66 MHz Shift Clock Support
  • feature
    50% Duty Cycle on Receiver Output Clock
  • feature
    Automotive AEC-Q100 Grade 2 Qualified
  • feature
    Bestu2013inu2013Class Setup & Hold Times on Rx Outputs
  • feature
    Compatible with TIA/EIA-644 LVDS Standard
  • feature
    ESD Rating: 4 kV (HBM), 1 kV (CDM)
  • feature
    Low Profile 56-Pin DGG (TSSOP) Package
  • feature
    Operating Temperature: u221240u00b0C to +105u00b0C
  • feature
    PLL Requires No External Components
  • feature
    Rx Power Consumption < 270 mW (typ) at 66 MHz Worst Case
  • feature
    Rx Power-down Mode < 200 u03bcW (max)

Description

LVDS RECEIVER TSSOP-56
The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge. The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps. The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-toRGB bridge conversion. LVDS data transmission over cable interconnect is not recommended for this device. Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1 receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found in the Application Information section.

Specifications

Device Type:
LVDS Receiver
Peak-to-Peak Jitter Max:
-
Supply Current Max:
1.8µA
Operating Temperature Min:
-40°C
Operating Temperature Max:
105°C
Supply Voltage Min:
3V
Supply Voltage Max:
3.6V
Driver Case Style:
TSSOP
No. of Pins:
56Pins
Signaling Rate:
462Mbps
Signal Input Type:
LVDS
Output Level Type:
LVCMOS
ESD HBM:
4kV
Product Range:
-
Automotive Qualification Standard:
AEC-Q100
RoHS Phthalates Compliant:
Yes
MSL:
MSL 2 - 1 year
SVHC:
No SVHC (27-Jun-2018)

Alternate Descriptions

Avnet America

LVDS Receiver 56-Pin TSSOP T/R

Avnet America product

Avnet Europe

LVDS Receiver 56-Pin TSSOP T/R

Avnet Europe product

Texas Instruments

3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Chan Link 66 MHz

Texas Instruments product