DS90CF366MTD/NOPB

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Price Comparison for DS90CF366MTD/NOPB
Details for Texas Instruments

DS90CF366MTD/NOPB

+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz
Buy Directly from Texas Instruments (7201 in Stock)
$3.6000 per unit
Series Information for DS90CF366MTD/NOPB - Texas Instruments

Features

  • feature
    20-MHz to 85-MHz Shift Clock Support
  • feature
    Compatible With TIA/EIA-644 LVDS Standard
  • feature
    DS90CF386 Also Available in a 64-Pin, 0.8-mm,
  • feature
    ESD Rating >7 kV (HBM), >700 V (EIAJ)
  • feature
    Low Profile 56-Pin or 48-Pin TSSOP Package
  • feature
    PLL Requires No External Components
  • feature
    Rx Power Consumption <142 mW (Typical) at 85-MHz Grayscale
  • feature
    Rx Power-Down Mode <1.44 mW (Maximum)
  • feature
    Supports VGA, SVGA, XGA, and Single Pixel SXGA

Description

LVDS LINE RECEIVER 2.38GBPS TSSOP-48
The DS90CF386 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CF366 receiver that converts three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the falling edge. A rising edge or falling edge strobe transmitter will interoperate with a falling edge strobe receiver without any translation logic. The receiver LVDS clock operates at rates from 20 MHz to 85 MHz. The device phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 85 MHz, each LVDS input line is running at a bit rate of 595 Mbps, resulting in a maximum throughput of 2.38 Gbps for the DS90CF386 and 1.785 Gbps for the DS90CF366. The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high-speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages. The DS90CF386 is also offered in a 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA) package which provides a 44% reduction in PCB footprint compared to the 56-pin TSSOP package.

Specifications

Device Type:
Differential Receiver
Peak-to-Peak Jitter Max:
250ps
Supply Current Max:
115mA
Operating Temperature Min:
-10°C
Operating Temperature Max:
70°C
Supply Voltage Min:
3V
Supply Voltage Max:
3.6V
Driver Case Style:
TSSOP
No. of Pins:
48Pins
Signaling Rate:
2.38Gbps
Signal Input Type:
LVDS
Output Level Type:
TTL
ESD HBM:
7kV
Product Range:
-
Automotive Qualification Standard:
-
RoHS Phthalates Compliant:
Yes
MSL:
MSL 2 - 1 year
SVHC:
No SVHC (27-Jun-2018)

Alternate Descriptions

Avnet America

LVDS Flat Panel Display 48-Pin TSSOP Rail

Avnet America product

Avnet Europe

LVDS Flat Panel Display 48-Pin TSSOP Rail

Avnet Europe product

Texas Instruments

+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz

Texas Instruments product

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