AD9777BSVZ

16-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2u00d7/4u00d7/8u00d7 interpolating filter Programmable channel gain and offset adjustment fS/4, fS/8 digital quadrature modulation capability Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fully compatible SPIu00ae port Excellent ac performance SFDR u221273 dBc @ 2 MHz to 35 MHz WCDMA ACPR 71 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible Versatile input data interface Twos complement/straight binary data coding Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.2 V reference 80-lead thin quad flat package, exposed pad (TQFP_EP)