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Series Information for AD9578BCPZ - Analog Devices


  • feature
    Any output frequency precision synthesis 11.8 MHz to 919 MHz Better than 0.1 ppb frequency resolution Ultralow rms jitter (12 kHz to 20 MHz) <300 fs rms using integer synthesis <405 fs rms using fractional synthesis Dual reference inputs support LVPECL, LVDS, 1.8 V LVCMOS, or fundamental mode AT cut crystals from 22 MHz to 54 MHz or reference clocks from 20 MHz to 60 MHz Numerical (NCO) frequency control Dynamically pullable output frequency enables FPGA- based PLLs (HDL available) Fast serial peripheral interface (SPI) bus write speeds up to 100 MHz On-the-fly frequency changes Dual PLL in compact 7 mm u00d7 7 mm package Replaces multiple large clock ICs, PLLs, fanout buffers, crystal oscillators (XOs), and voltage controlled crystal oscillators (VCXOs) Mix and match output buffers In-circuitprogrammable LVPECL/LVDS/HCSL/LVCMOS Independent buffer (VDDOx) drives multiple technologies Enhanced power supply noise rejection



The AD9578 is a programmable synthesizer intended for jitter attenuation and asynchronous clocking applications in high performance telecommunications, networking, data storage, serializer/deserializer (SERDES), and physical layer (PHY) applications. The device incorporates two low jitter PLLs that provide any frequency with precision better than 0.1 ppb, each with two separate output dividers, for a total of four programmable outputs, delivering maximum flexibility and jitter performance. Each output is independently programmable to provide frequen- cies of up to 919 MHz with <410 fs typical rms jitter (12 kHz to 20 MHz) utilizing compact, low cost fundamental mode crystals (XTALs) that enable a robust supply chain. Using integer frequency synthesis, the AD9578 is capable of achieving rms jitter as low as 290 fs. The AD9578 is packaged with a factory programmed default power-on configuration. After power-on, all settings including output frequency are reconfigurable through a fast SPI. The AD9578 architecture permits it to be used as a numerically controlled oscillator (NCO). This allows the user to dynamically change the frequency using the fast SPI bus. FPGAs and other devices can take advantage of this function to implement digital PLLs with configurable loop bandwidths for jitter attenuation applications, precision disciplined clocks that lock to tight stability references, or digitally controlled precision timing applications, such as network timing and IEEE 1588 applications. The SPI bus can operate up to 50 MHz, enabling fast FPGA loops while multiple devices share the same bus. The AD9578 can also be used in multirate precision applications, such as broadcast video or OTN. HDL FPGA code for digital PLL applications is available from Analog Devices, Inc.


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RoHS Phthalates Compliant:
MSL 3 - 168 hours
No SVHC (07-Jul-2017)