Series Information for AD6649BCPZ - Analog Devices
Features
SNR = 73.0 dBFS in a 95 MHz bandwidth at
185 MHz AIN and 245.76 MSPS
SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
Noise density = u2212151.2 dBFS/Hz input at 185 MHz, u22121 dBFS
AIN and 250 MSPS
Total power consumption: 1 W with fixed-frequency NCO, 95 MHz FIR filter
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Integrated dual-channel ADC
Sample rates of up to 250 MSPS
IF sampling frequencies to 400 MHz
Internal ADC voltage reference
Flexible input range
1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital processor
32-bit complex numerically controlled oscillator (NCO)
FIR filter with 2 modes
Real output from an fS/4 output NCO
Amplitude detect bits for efficient AGC implementation
Energy saving power-down modes
Decimated, interleaved real LVDS data outputs
The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC). The AD6649 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
