Series Information for AD4003BRMZ - Analog Devices
Features
Throughput: 2 MSPS maximum
INL: u00b11.0 LSB (u00b13.8 ppm) maximum
Guaranteed 18-bit no missing codes
Low power
9.5 mW at 2 MSPS (VDD only)
80 u00b5W at 10 kSPS, 16 mW at 2 MSPS (total)
SNR: 100.5 dB typical at 1 kHz, 99 dB typical at 100 kHz
THD: u2212123 dB typical at 1 kHz, u2212100 dB typical at 100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Differential analog input range: u00b1VREF
0 V to VREF with VREF between 2.4 V to 5.1 V
Single 1.8V supply operation with 1.71V to 5.5V logic interface
SAR architecture: no latency/pipeline delay
Guaranteed operation: u221240u00b0C to 125u00b0C
Serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead package: 3 mm u00d7 3 mm LFCSP and 3 mm u00d7 4.90 mm
MSOP
The AD4003 is a low noise, low power, high speed, 18-bit, 2 MSPS precision successive approximation register (SAR) analog-to- digital converter (ADC). It incorporates ease of use features that lower the signal chain power, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive this ADC directly, while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface (SPI) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. Operating from a 1.8 V supply, the AD4003 has a ±VREF fully differ- ential input range with VREF ranging from 2.4 V to 5.1 V. The AD4003 consumes only 16 mW at 2 MSPS with a minimum of 75 MHz SCK rate in turbo mode and achieves ±1.0 LSB (±3.8 ppm) INL maximum, guaranteed no missing codes at 18 bits with 100.5 dB typical SNR. The reference voltage is applied externally and can be set independently of the supply voltage. The SPI-compatible versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. The AD4003 is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD4003 is available in a 10-lead MSOP or a 10-lead LFCSP with operation specified from −40°C to +125°C. The device is pin compatible with the 16-bit, 2 MSPS AD4000.
