Overview: This article discusses RISC-V, an open-source instruction set that helps create customizable and efficient processors for embedded systems, promoting teamwork and technological innovation.

The main functions of a processor are to fetch, decode, execute, and write back. The processor fetches instructions from memory, decodes the instruction to determine the necessary operations, executes the operation, and then writes back the results based on the instruction set architecture (ISA).

What is an ISA?

ISA is an important component of processor architecture that serves as the interface between hardware and software. It defines an entire group of commands a processor can perform to execute the program instruction. 

Based on the instruction set, computer architecture is primarily classified into two types: 

  • Complex Instruction Set Computer (CISC)
  • Reduced Instruction Set Computer (RISC)

Complex Instruction Set Computer (CISC)

CISC architecture emerged in the 1960s and 1970s when memory was slow and expensive. The goal was to bridge the gap between high-level languages (HLL) and machine-level instructions by allowing complex operations to be executed with single, intricate instructions. CISC enables programmers to perform multi-step operations within a single command.

This approach reduced the burden on compilers but increased the complexity of processor design. The CISC instructions require more complex hardware designs and decoding mechanisms, which can lead to increased manufacturing costs. These instructions often take longer to decode and execute, leading to higher power consumption and heat generation.

Reduced Instruction Set Computer (RISC)

RISC architecture is an alternative processor technology that focuses on simple instructions that are executed frequently. It is a major competitor to the closed ISA architecture commonly deployed in microcontrollers and embedded devices.

While CISC architectures could complete tasks in a single complex instruction, RISC architectures typically require multiple simple instructions to perform the same task. Most RISC architectures are designed to execute one instruction per clock cycle. The simplicity of RISC instructions facilitates effective pipelining, where multiple instruction phases (fetch, decode, execute) can occur simultaneously. This leads to improved overall processor performance.

CISC architectures require a large number of transistors to support complex instructions. In contrast, RISC architectures simplify the hardware implementation due to their reduced instruction set. This saving in transistor space is then utilized to increase the number of registers, cache memory, and math co-processors. With an increased number of registers, RISC processors do not need to access main memory as frequently as CISC processors. Fig. 1 provides a comparison of CISC and RISC architectures.

Fig. 1 Comparison of CISC Vs. RISC architectures. Source: Rakesh Kumar, Ph.D.

X86 Vs. ARM Vs. RISC-V

Due to its open-access nature, RISC-V distinguishes it from proprietary architectures like x86 and ARM. 

  • Intel and AMD exclusively have licensing agreements to manufacture and sell the x86 family of processors commonly used in desktops, laptops, and servers.
  • ARM has a broader licensing model allowing multiple manufacturers to create ARM-based processors used in Android, iOS, and Apple computers, paying licensing fees to ARM Holdings.
  • In contrast, RISC-V is a free and open ISA that allows anyone to design, implement, and sell RISC-V processors without any licensing constraint. RISC-V is the potential competitor to ARM and x86 in end-user and server computing. Fig. 2 provides the comparative analysis of X86 Vs. ARM Vs. RISC-V.

Fig. 2 Comparison of X86 Vs. ARM Vs. RISC-V architectures. Source: Rakesh Kumar, Ph.D.

Exploring RISC-V

RISC-V is the fifth generation of RISC architecture developed at the University of California, Berkeley. Initially, it started as a three-month project to support computer architecture for research and education purposes. RISC-V has now evolved into a significant free standard open architecture ISA governed by a non-profit organization called RISC-V International, based in Switzerland. 

RISC-V has many applications, including artificial intelligence, cloud computing, edge computing, the Internet of Things, industrial applications, etc. Designers of RISC-V cores and chips have the unique advantage of deciding whether the intellectual property (IP) they create will be placed in the public domain or licensed commercially.

The base integer ISA is present for every RISC-V implementation. It provides a core set of instructions necessary for basic computational tasks, enabling the development of compilers, assemblers, linkers, and operating systems. Additionally, RISC V architecture comprises both standard and non-standard extensions.

Standard extensions are predefined instructions that enhance the base integer ISA, which include multiplication and division, atomic operations, single or double-precision floating-point, compressed instructions, vector operations etc.

Non-standard extensions are highly specialized and customized instructions that developers can define based on specific application needs. These extensions allow for domain-specific optimizations and can introduce unique capabilities to particular workloads. These extensions do not break compatibilities with the main RISC-V specifications. 

Advantages

  • RISC-V is a high-quality, open-access ISA, allowing users to implement and modify it without licensing fees or royalties contrast with closed ISAs like x86 and ARM.
  • The architecture with a reduced instruction set leads to fewer transistors being used for complex instructions, enabling more registers and cache memory to be integrated.
  • Its flexibility enables RISC-V to be highly employed in embedded systems and a wide range of computing systems, from microcontrollers to supercomputers.
  • RISC-V ISA has become more popular because it is an open standard that can be used in any hardware technology (for example, ASIC or FPGA) and can be customized easily.
  • RISC-V employs a pipelined execution model that breaks down instruction execution into multiple stages—fetching, decoding, executing, memory access, and writing back results.
  • RISC-V is a royalty-free program with reduced deployment costs for developing embedded systems in real-time situations.

RISC-V represents a significant shift in processor design from embedded systems to high-performance computing environments, making it a promising competitor in the semiconductor industry.

Summarizing the Key Points

  • RISC-V is an open-source instruction set architecture that facilitates the creation of customizable and efficient processors for various embedded system applications.
  • Compared to traditional ISAs like x86 and ARM, RISC-V is a free and open ISA that allows anyone to design, implement, and sell RISC-V processors without any licensing constraint.
  • RISC-V's reduced instruction set simplifies hardware design, enabling more efficient use of transistors, which enhances the integration of registers and cache memory in processors.

Reference

Coluccio, A., Ieva, A., Riente, F., Roch, M. R., Ottavi, M., & Vacca, M. (2022). RISC-VLIM, a RISC-V framework for Logic-in-Memory architectures. Electronics, 11(19), 2990.
https://doi.org/10.3390/electronics11192990

Yoo, T., & Choi, B. W. (2024). Real-Time performance benchmarking of RISC-V architecture: implementation and verification on an EtherCAT-Based robotic control system. Electronics, 13(4), 733. https://doi.org/10.3390/electronics13040733

Dakić, V., Mršić, L., Kunić, Z., & Đambić, G. (2024). Evaluating ARM and RISC-V Architectures for High-Performance Computing with Docker and Kubernetes. Electronics, 13(17), 3494. https://doi.org/10.3390/electronics13173494